FM3164-STR Ramtron, FM3164-STR Datasheet - Page 16

• Manufacturer Part Number: FM3164-STR
• Description: case, leaded, supervisor, reflow, soic, supply, process, max, ram, Interface ICs, package, compatible, voltage, memor...
• Manufacturer: Ramtron

Slave Address
The first byte that the FM31xx expects after a Start
condition is the slave address. As shown in figures
below, the slave address contains the Slave ID,
Device Select address, and a bit that specifies if the
transaction is a read or a write.
The FM31xx has two Slave Addresses (Slave IDs)
associated with two logical devices. To access the
memory device, bits 7-4 should be set to 1010b. The
other logical device within the FM31xx is the real-
time clock and companion. To access this device,
bits 7-4 of the slave address should be set to 1101b.
A bus transaction with this slave address will not
affect the memory in any way. The figures below
illustrate the two Slave Addresses.
The Device Select bits allow multiple devices of the
same type to reside on the 2-wire bus. The device
select bits (bits 2-1) select one of four parts on a two-
wire bus. They must match the corresponding value
on the external address pins in order to select the
device. Bit 0 is the read/write bit. A “1” indicates a
read operation, and a “0” indicates a write operation.
Addressing Overview – Memory
After the FM31xx acknowledges the Slave Address,
the master can place the memory address on the bus
for a write operation. The address requires two bytes.
This is true for all members of the family. Therefore
the 4Kb and 16Kb configurations will be addressed
differently from stand alone serial memories but the
entire family will be upwardly compatible with no
software changes.
The first is the MSB (upper byte). For a given
density unused address bits are don’t cares, but
should be set to 0 to maintain upward compatibility.
Rev. 2.3
Oct. 2006
7
7
1
1
Figure 10. Slave Address – Companion
Slave ID
Figure 9. Slave Address - Memory
Slave ID
0
1
6
6
5
5
1
0
4
4
0
1
3
3
X
X
A1
A1
2
2
Device
Device
Select
Select
A0
A0
1
1
R/W
R/W
0
0
Following the MSB is the LSB (lower byte) which
contains the remaining eight address bits. The
address is latched internally. Each access causes the
latched address to be incremented automatically. The
current address is the value that is held in the latch,
either a newly written value or the address following
the last access. The current address will be held as
long as VDD > VTP or until a new value is written.
Accesses to the clock do not affect the current
memory address. Reads always use the current
address. A random read address can be loaded by
beginning a write operation as explained below.
After transmission of each data byte, just prior to the
Acknowledge, the FM31xx increments the internal
address. This allows the next sequential byte to be
accessed with no additional addressing externally.
After the last address is reached, the address latch
will roll over to 0000h. There is no limit to the
number of bytes that can be accessed with a single
read or write operation.
Addressing Overview – RTC & Companion
The RTC and Processor Companion operate in a
similar manner to the memory, except that it uses
only one byte of address. Addresses 00h to 18h
correspond to special function registers. Attempting
to load addresses above 18h is an illegal condition;
the FM31xx will return a NACK and abort the 2-
wire transaction.
Data Transfer
After the address information has been transmitted,
data transfer between the bus master and the
FM31xx begins. For a read, the FM31xx will place 8
data bits on the bus then wait for an ACK from the
master. If the ACK occurs, the FM31xx will transfer
the next byte. If the ACK is not sent, the FM31xx
will end the read operation. For a write operation, the
FM31xx will accept 8 data bits from the master then
send an Acknowledge. All data transfer occurs MSB
(most significant bit) first.
Memory Write Operation
All memory writes begin with a Slave Address, then
a memory address. The bus master indicates a write
operation by setting the slave address LSB to a 0.
After addressing, the bus master sends each byte of
data to the memory and the memory generates an
Acknowledge condition. Any number of sequential
bytes may be written. If the end of the address range
is reached internally, the address counter will wrap
to 0000h. Internally, the actual memory write occurs
after the 8
before the Acknowledge is sent. Therefore, if the
th
data bit is transferred. It will be complete
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