FM3164-STR Ramtron, FM3164-STR Datasheet - Page 13

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FM3164-STR

Manufacturer Part Number
FM3164-STR
Description
case, leaded, supervisor, reflow, soic, supply, process, max, ram, Interface ICs, package, compatible, voltage, memor...
Manufacturer
Ramtron
Datasheet
Rev. 2.3
Oct. 2006
09h
WTR
POR
LB
WR3-0
08h
07h
06h
05h
04h
03h
02h
Watchdog Restart & Flags
Watchdog Timer Reset Flag: When the /RST signal is activated by the watchdog the WTR bit will be set to 1. It
must be cleared by the user. Note that both WTR and POR could be set if both reset sources have occurred since
the flags were cleared by the user. Battery-backed. Read/Write (internally set, user can clear bit).
Power-on Reset Flag: When the /RST pin is activated by either V
set to 1. It must be cleared by the user. Note that both WTR and POR could be set if both reset sources have
occurred since the flags were cleared by the user. Battery-backed. Read/Write (internally set, user can clear bit).
Low Backup Flag: On power up, if the VBAK source is below the minimum voltage to operate the RTC and event
counters, this bit will be set to 1. The user should clear it to 0 when initializing the system. Battery-backed.
Read/Write (internally set, user can clear bit).
Watchdog Restart: Writing a pattern 1010b to WR3-0 restarts the watchdog timer. The upper nibble contents do
not affect this operation. Writing any pattern other than 1010b to WR3-0 has no effect on the timer. This allows
users to clear the WTR, POR, and LB flags without affecting the watchdog timer. Battery-backed, Write-only.
Timekeeping – Years
Contains the lower two BCD digits of the year. Lower nibble contains the value for years; upper nibble contains
the value for 10s of years. Each nibble operates from 0 to 9. The range for the register is 0-99. Battery-backed,
read/write.
Timekeeping – Months
Contains the BCD digits for the month. Lower nibble contains the lower digit and operates from 0 to 9; upper
nibble (one bit) contains the upper digit and operates from 0 to 1. The range for the register is 1-12. Battery-
backed, read/write.
Timekeeping – Date of the month
Contains the BCD digits for the date of the month. Lower nibble contains the lower digit and operates from 0 to 9;
upper nibble contains the upper digit and operates from 0 to 3. The range for the register is 1-31. Battery-backed,
read/write.
Timekeeping – Day of the week
Lower nibble contains a value that correlates to day of the week. Day of the week is a ring counter that counts
from 1 to 7 then returns to 1. The user must assign meaning to the day value, as the day is not integrated with the
date. Battery-backed, read/write.
Timekeeping – Hours
Contains the BCD value of hours in 24-hour format. Lower nibble contains the lower digit and operates from 0 to
9; upper nibble (two bits) contains the upper digit and operates from 0 to 2. The range for the register is 0-23.
Battery-backed, read/write.
Timekeeping – Minutes
Contains the BCD value of minutes. Lower nibble contains the lower digit and operates from 0 to 9; upper nibble
contains the upper minutes digit and operates from 0 to 5. The range for the register is 0-59. Battery-backed,
read/write.
Timekeeping – Seconds
Contains the BCD value of seconds. Lower nibble contains the lower digit and operates from 0 to 9; upper nibble
contains the upper digit and operates from 0 to 5. The range for the register is 0-59. Battery-backed, read/write.
10 year.3
WTR
D7
D7
D7
D7
D7
D7
D7
D7
0
0
0
0
0
0
10 year.2
10 min.2
10 sec.2
POR
D6
D6
D6
D6
D6
D6
D6
D6
0
0
0
0
10 hours.1
10 year.1
10 date.1
10 min.1
10 sec.1
D5
D5
D5
D5
D5
D5
D5
D5
LB
0
0
10 hours.0
10 Month
10 year.0
10 date.0
10 min.0
10 sec.0
D4
D4
D4
D4
D4
D4
D4
D4
0
-
Seconds.3
Month.3
Hours.3
Year.3
Date.3
Min.3
WR3
D3
D3
D3
D3
D3
D3
D3
D3
0
DD
< V
TP
Seconds.2
Month.2
or a manual reset, the POR bit will be
Hours2
Year.2
Date.2
Day.2
Min.2
WR2
D2
D2
D2
D2
D2
D2
D2
D2
Seconds.1
Month.1
Hours.1
Date.1
Year.1
Day.1
Min.1
WR1
D1
D1
D1
D1
D1
D1
D1
D1
FM3104/16/64/256
Page 13 of 25
Seconds.0
Month.0
Hours.0
Date.0
Year.0
Day.0
Min.0
WR0
D0
D0
D0
D0
D0
D0
D0
D0

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