IS46TR16128A-125KBLA1-TR ISSI, IS46TR16128A-125KBLA1-TR Datasheet - Page 16

• Manufacturer Part Number: IS46TR16128A-125KBLA1-TR
• Description: DRAM 2G, 1.5V, 1600MT/s 128Mx16 DDR3
• Manufacturer: ISSI

Specifications of IS46TR16128A-125KBLA1-TR

• Rohs: yes
• Data Bus Width: 16 bit
• Organization: 128 M x 16
• Package / Case: FBGA-96
• Memory Size: 2 Gbit
• Maximum Clock Frequency: 933 MHz
• Access Time: 13.125 ns
• Supply Voltage - Max: 1.575 V
• Supply Voltage - Min: 1.425 V
• Maximum Operating Current: 70 mA
• Maximum Operating Temperature: + 95 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT

IS43/46TR16128A, IS43/46TR16128AL,
IS43/46TR82560A, IS43/46TR82560AL
2.3.4.4 Dynamic ODT (Rtt_WR)
DDR3 SDRAM introduces a new feature “Dynamic ODT”. In certain application cases and to further enhance signal
integrity on the data bus, it is desirable that the termination strength of the DDR3 SDRAM can be changed without issuing
an MRS command. MR2 Register locations A9 and A10 configure the Dynamic ODT setings. In Write leveling mode, only
RTT_Nom is available. For details on Dynamic ODT operation, refer to “Dynamic ODT”.
2.3.5 Mode Register MR3
The Mode Register MR3 controls Multi-purpose registers. The Mode Register 3 is written by asserting low on CS#, RAS#,
CAS#, WE#, high on BA1 and BA0, and low on BA2 while controlling the states of address pins according to the below.
* 1 : A3 - A14 must be programmed to 0 during MRS.
* 2 : The predefined pattern will be used for read synchronization.
* 3 : When MPR control is set for normal operation (MR3 A[2] = 0) then MR3 A[1:0] will be ignored
2.3.5.1 Multi-Purpose Register (MPR)
The Multi Purpose Register (MPR) function is used to Read out a predefined system timing calibration bit sequence. To
enable the MPR, a Mode Register Set (MRS) command must be issued to MR3 register with bit A2=1. Prior to issuing the
MRS command, all banks must be in the idle state (all banks precharged and tRP met). Once the MPR is enabled, any
subsequent RD or RDA commands will be redirected to the Multi Purpose Register. When the MPR is enabled, only RD
or RDA commands are allowed until a subsequent MRS command is issued with the MPR disabled (MR3 bit A2=0).
Power down mode, Self-Refresh and any other non-RD/RDA command is not allowed during MPR enable mode. The
RESET function is supported during MPR enable mode.
The Multi Purpose Register (MPR) function is used to Read out a predefined system timing calibration bit sequence. The
basic concept of the MPR is shown in Figure 2.3.5.1.
Integrated Silicon Solution, Inc. – www.issi.com –
Rev. 00A
11/14/2012
MRP Operation
BA1 BA0
BA2 BA1 BA0
A2
0
0
1
0
0
1
1
1
0
1
0
1
1
Dataflow from MPR
Normal operation
MR Select
MR0
MR1
MR2
MR3
MPR
A14-A13
*3
A12
A11
A10
Figure 2.3.5 MR3 Definition
MPR Address
0*
A9
A1
0
0
1
1
1
A8
A0
0
1
0
1
A7
A6
A5
Predefined pattern
MPR location
A4
.
RFU
RFU
RFU
A3
MPR
*2
A2
A1
MPR Loc
A0
Address Field
Mode Register 3
16