IS46TR16128A-125KBLA1-TR ISSI, IS46TR16128A-125KBLA1-TR Datasheet - Page 74

• Manufacturer Part Number: IS46TR16128A-125KBLA1-TR
• Description: DRAM 2G, 1.5V, 1600MT/s 128Mx16 DDR3
• Manufacturer: ISSI

Specifications of IS46TR16128A-125KBLA1-TR

• Rohs: yes
• Data Bus Width: 16 bit
• Organization: 128 M x 16
• Package / Case: FBGA-96
• Memory Size: 2 Gbit
• Maximum Clock Frequency: 933 MHz
• Access Time: 13.125 ns
• Supply Voltage - Max: 1.575 V
• Supply Voltage - Min: 1.425 V
• Maximum Operating Current: 70 mA
• Maximum Operating Temperature: + 95 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT

IS43/46TR16128A, IS43/46TR16128AL,
IS43/46TR82560A, IS43/46TR82560AL
9.6 Data Setup, Hold and Slew Rate Derating
For all input signals the total tDS (setup time) and tDH (hold time) required is calculated by adding the data sheet
tDS(base) and tDH(base) value (see Table 72) to the tDS and tDH (see Table 73) derating value respectively. Example:
tDS (total setup time) = tDS(base) + tDS.
Setup (tDS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VREF(dc) and the
first crossing of V IH(ac) min. Setup (tDS) nominal slew rate for a falling signal is defined as the slew rate between the last
crossing of VREF(dc) and the first crossing of VIL(ac) max. If the actual signal is always earlier than the nominal slew rate
line between shaded ‘VREF(dc) to ac region’, use nominal slew rate for derating value. If the actual signal is later than the
nominal slew rate line anywhere between shaded ‘VREF(dc) to ac region’, the slew rate of a tangent line to the actual
signal from the ac level to VREF(dc) level is used for derating value.
Hold (tDH) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VIL(dc) max and
the first crossing of VREF(dc) . Hold (tDH) nominal slew rate for a falling signal is defined as the slew rate between the
last crossing of VIH(dc) min and the first crossing of VREF(dc). If the actual signal is always later than the nominal slew
rate line between shaded ‘dc level to VREF(dc) region’, use nominal slew rate for derating value. If the actual signal is
earlier than the nominal slew rate line anywhere between shaded ‘dc to V REF(dc) region’, the slew rate of a tangent line
to the actual signal from the dc level to VREF(dc) level is used for derating value.
For a valid transition the input signal has to remain above/below VIH/IL(ac) for some time tVAC.
Although for slow slew rates the total setup time might be negative (i.e. a valid input signal will not have reached VIH/IL(ac)
at the time of the rising clock transition) a valid input signal is still required to complete the transition and reach VIH/IL(ac) .
For slew rates in between the values listed in the tables the derating values may obtained by linear interpolation.
These values are typically not subject to production test. They are verified by design and characterization.
9.6.1 Data Setup and Hold Base-Values
NOTE: (ac/dc referenced for 1V/ns DQ-slew rate and 2 V/ns DQS slew rate)
Integrated Silicon Solution, Inc. – www.issi.com –
Rev. 00A
11/14/2012
tDS(base) AC175
tDS(base) AC150
tDH(base) DC100
tDS(base) AC160
tDS(base) AC135
tDH(base) DC90
Symbol
Symbol
Reference
Reference
VIH/L(ac)
VIH/L(ac)
VIH/L(dc)
VIH/L(ac)
VIH/L(ac)
VIH/L(dc)
DDR3L-800
DDR3-800
125
150
140
160
75
90
DDR3L-1066
DDR3-1066
100
110
25
75
40
90
DDR3L-1333
DDR3-1333
30
65
45
75
-
-
DDR3L-1600
DDR3-1600
10
45
25
55
-
-
Units
Units
ps
ps
ps
ps
ps
ps
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