IS46TR16128A-125KBLA1-TR ISSI, IS46TR16128A-125KBLA1-TR Datasheet - Page 71

• Manufacturer Part Number: IS46TR16128A-125KBLA1-TR
• Description: DRAM 2G, 1.5V, 1600MT/s 128Mx16 DDR3
• Manufacturer: ISSI

Specifications of IS46TR16128A-125KBLA1-TR

• Rohs: yes
• Data Bus Width: 16 bit
• Organization: 128 M x 16
• Package / Case: FBGA-96
• Memory Size: 2 Gbit
• Maximum Clock Frequency: 933 MHz
• Access Time: 13.125 ns
• Supply Voltage - Max: 1.575 V
• Supply Voltage - Min: 1.425 V
• Maximum Operating Current: 70 mA
• Maximum Operating Temperature: + 95 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT

IS43/46TR16128A, IS43/46TR16128AL,
IS43/46TR82560A, IS43/46TR82560AL
9.5 Address / Command Setup, Hold and Derating
For all input signals the total tIS (setup time) and tIH (hold time) required is calculated by adding the datasheet tIS(base)
and tIH(base) value to the tIS and tIH derating value respectively. Example: tIS (total setup time) = tIS(base) + tIS
Setup (tIS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VREF(dc) and the
first crossing of VIH(ac)min. Setup (tIS) nominal slew rate for a falling signal is defined as the slew rate between the last
crossing of VREF(dc) and the first crossing of Vil(ac)max. If the actual signal is always earlier than the nominal slew rate
line between shaded ‘VREF(dc) to ac region’, use nominal slew rate for derating value . If the actual signal is later than
the nominal slew rate line anywhere between shaded ‘VREF(dc) to ac region’, the slew rate of a tangent line to the actual
signal from the ac level to VREF (dc) level is used for derating value.
Hold (tIH) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of Vil(dc)max and the
first crossing of VREF(dc). Hold (tIH) nominal slew rate for a falling signal is defined as the slew rate between the last
crossing of Vih(dc)min and the first crossing of VREF(dc). If the actual signal is always later than the nominal slew rate
line between shaded ‘dc to VREF(dc) region’, use nominal slew rate for derating value. If the actual signal is earlier than
the nominal slew rate line anywhere between shaded ‘dc to VREF(dc) region’, the slew rate of a tangent line to the actual
signal from the dc level to VREF (dc) level is used for derating value.
For a valid transition the input signal has to remain above/below VIH/IL(ac) for some time tVAC. Although for slow slew
rates the total setup time might be negative (i.e. a valid input signal will not have reached VIH/IL(ac) at the time of the
rising clock transition, a valid input signal is still required to complete the transition and reach VIH/IL(ac). For slew rates in
between the values listed in Table 69, the derating values may obtained by linear interpolation.
These values are typically not subject to production test. They are verified by design and characterization.
9.5.1 ADD/CMD Setup and Hold Base-Values for 1V/ns
Notes:
1. (ac/dc referenced for 1V/ns Address/Command slew rate and 2 V/ns differential CK-CK# slew rate)
2. The tIS(base) AC150 specifications are adjusted from the tIS(base) AC175 specification by adding an additional 125 ps for DDR3-800/1066 or
Integrated Silicon Solution, Inc. – www.issi.com –
Rev. 00A
11/14/2012
tIH(base) DC100
tIS(base) AC175
tIS(base) AC150
tIS(base) AC160
tIS(base) AC135
tIH(base) DC90
100ps for DDR3-1333/1600 of derating to accommodate for the lower alternate threshold of 150 mV and another 25 ps to account for the earlier
reference point [(175 mv - 150 mV) / 1 V/ns].
Symbol
Symbol
Reference
Reference
VIH/L(ac)
VIH/L(ac)
VIH/L(dc)
VIH/L(ac)
VIH/L(ac)
VIH/L(dc)
DDR3L-800
DDR3-800
200
350
275
215
365
285
DDR3L-1066
DDR3-1066
125
275
200
140
290
210
DDR3L-1333
DDR3-1333
190
140
205
150
65
80
DDR3L-1600
DDR3-1600
170
120
185
130
45
60
Units
Units
ps
ps
ps
ps
ps
ps
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