IS46TR16128A-125KBLA1-TR ISSI, IS46TR16128A-125KBLA1-TR Datasheet - Page 24

• Manufacturer Part Number: IS46TR16128A-125KBLA1-TR
• Description: DRAM 2G, 1.5V, 1600MT/s 128Mx16 DDR3
• Manufacturer: ISSI

Specifications of IS46TR16128A-125KBLA1-TR

• Rohs: yes
• Data Bus Width: 16 bit
• Organization: 128 M x 16
• Package / Case: FBGA-96
• Memory Size: 2 Gbit
• Maximum Clock Frequency: 933 MHz
• Access Time: 13.125 ns
• Supply Voltage - Max: 1.575 V
• Supply Voltage - Min: 1.425 V
• Maximum Operating Current: 70 mA
• Maximum Operating Temperature: + 95 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT

IS43/46TR16128A, IS43/46TR16128AL,
IS43/46TR82560A, IS43/46TR82560AL
2.4.5 DLL on/off switching procedure
DDR3 DLL-off mode is entered by setting MR1 bit A0 to “1”; this will disable the DLL for subsequent operation until A0 bit
set back to “0”.
2.4.5.1 DLL “on” to DLL “off” Procedure
To switch from DLL “on” to DLL “off” requires te frequency to be changed during Self-Refresh outlined in the following
procedure:
2.4.5.2 DLL “off” to DLL “on” Procedure
To switch from DLL “off” to DLL “on” (with required frequency change) during Self-Refresh:
Integrated Silicon Solution, Inc. – www.issi.com –
Rev. 00A
11/14/2012
1. Starting from Idle state (all banks pre-charged, all timing fulfilled, and DRAMs On-die Termination resistors, RTT,
2. Set MR1 Bit A0 to “1” to disable the DLL.
3. Wait tMOD.
4. Enter Self Refresh Mode; wait until (tCKSRE) satisfied.
5. Change frequency, in guidance with “Input Clock Frequency Change” section.
6. Wait until a stable clock is available for at least (tCKSRX) at DRAM inputs.
7. Starting with the Self Refresh Exit command, CKE must continuously be registered HIGH until all tMOD timings from
8. Wait tXS, and then set Mode Registers with appropriate values (especially an update of CL, CWL, and WR may be
9. Wait for tMOD, and then DRAM is ready for next command.
1. Starting from Idle state (All banks pre-charged, all timings fulfilled and DRAMs On-die Termination resistors (RTT)
2. Enter Self Refresh Mode, wait until tCKSRE satisfied.
3. Change frequency, in guidance with "Input clock frequency change".
4. Wait until a stable clock is available for at least (tCKSRX) at DRAM inputs.
5. Starting with the Self Refresh Exit command, CKE must continuously be registered HIGH until tDLLK timing from
6. Wait tXS, then set MR1 bit A0 to “0” to enable the DLL.
7. Wait tMRD, then set MR0 bit A8 to “1” to start DLL Reset.
8. Wait tMRD, then set Mode Registers with appropriate values (especially an update of CL, CWL and WR may be
9. Wait for tMOD, then DRAM is ready for next command (Remember to wait tDLLK after DLL Reset before applying
must be in high impedance state before MRS to MR1 to disable the DLL).
any MRS command are satisfied. In addition, if any ODT features were enabled in the mode registers when Self
Refresh mode was entered, the ODT signal must continuously be registered LOW until all tMOD timings from any
MRS command are satisfied. If both ODT features were disabled in the mode registers when Self Refresh mode was
entered, ODT signal can be registered LOW or HIGH.
necessary. A ZQCL command may also be issued after tXS).
must be in high impedance state before Self-Refresh mode is entered.)
subsequent DLL Reset command is satisfied. In addition, if any ODT features were enabled in the mode registers
when Self Refresh mode was entered, the ODT signal must continuously be registered LOW until tDLLK timings from
subsequent DLL Reset command is satisfied. If both ODT features are disabled in the mode registers when Self
Refresh mode was entered, ODT signal can be registered LOW or HIGH.
necessary. After tMOD satisfied from any proceeding MRS command, a ZQCL command may also be issued during
or after tDLLK.)
command requiring a locked DLL!). In addition, wait also for tZQoper in case a ZQCL command was issued.
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