SSTUH32866EC/G,557 NXP Semiconductors, SSTUH32866EC/G,557 Datasheet - Page 13
![IC BUFFER 1.8V 25BIT SOT536-1](/photos/7/6/70664/96-lfbga_sot536-1_pkg_sml.jpg)
SSTUH32866EC/G,557
Manufacturer Part Number
SSTUH32866EC/G,557
Description
IC BUFFER 1.8V 25BIT SOT536-1
Manufacturer
NXP Semiconductors
Datasheet
1.SSTUH32866ECG518.pdf
(28 pages)
Specifications of SSTUH32866EC/G,557
Logic Type
1:1, 1:2 Configurable Registered Buffer with Parity
Supply Voltage
1.7 V ~ 1.9 V
Number Of Bits
25, 14
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
96-LFBGA
Logic Family
SSTU
Logical Function
Registered Buffer
Number Of Elements
1
Number Of Inputs
25
Number Of Outputs
25
High Level Output Current
-12mA
Low Level Output Current
12mA
Package Type
LFBGA
Propagation Delay Time
3ns
Operating Supply Voltage (typ)
1.8V
Operating Supply Voltage (max)
1.9V
Operating Supply Voltage (min)
1.7V
Clock-edge Trigger Type
Posit/Negat-Edge
Polarity
Non-Inverting
Technology
CMOS
Frequency (max)
450(Min)MHz
Mounting
Surface Mount
Pin Count
96
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
935277966557
SSTUH32866EC/G
SSTUH32866EC/G
SSTUH32866EC/G
SSTUH32866EC/G
Philips Semiconductors
Table 8:
At recommended operating conditions (see
[1]
[2]
[3]
Table 9:
At recommended operating conditions (see
[1]
[2]
Table 10:
At recommended operating conditions (see
9397 750 14199
Product data sheet
Symbol
f
t
t
t
t
t
Symbol
f
t
t
t
t
t
t
t
Symbol
dV/dt_r
dV/dt_f
dV/dt_
clock
W
ACT
INACT
su
h
MAX
PDM
PD
LH
HL
PDMSS
PHL
PLH
This parameter is not necessarily production tested.
VREF must be held at a valid input voltage level and data inputs must be held LOW for a minimum time of t
HIGH.
VREF, data and clock inputs must be held at valid levels (not floating) a minimum time of t
Includes 350 ps of test-load transmission line delay.
This parameter is not necessarily production tested.
Parameter
clock frequency
pulse duration, CK, CK HIGH
or LOW
differential inputs active time
differential inputs inactive time
setup time
hold time
Parameter
maximum input clock frequency
propagation delay, single bit switching
propagation delay
LOW-to-HIGH propagation delay
HIGH-to-LOW propagation delay
propagation delay,
simultaneous switching
HIGH-to-LOW propagation delay
LOW-to-HIGH propagation delay
Timing requirements
Switching characteristics
Data output edge rates
Parameter
rising edge slew rate
falling edge slew rate
absolute difference between dV/dt_r
and dV/dt_f
Table
Table
Table
Conditions
DCS before CK , CK , CSR HIGH; CSR
before CK , CK , DCS HIGH
DCS before CK , CK , CSR LOW
DODT, DCKE and data (Dn) before CK ,
CK
PAR_IN before CK , CK
DCS, DODT, DCKE and data (Dn) after
CK , CK
PAR_IN after CK , CK
1.8 V high-drive DDR2 configurable registered buffer with parity
6), unless otherwise specified. See
6), unless otherwise specified. See
6), unless otherwise specified. See
Rev. 01 — 13 May 2005
Conditions
from 20 % to 80 %
from 80 % to 20 %
from 20 % or 80 %
to 80 % or 20 %
Conditions
from CK and CK to Qn
from CK and CK to PPO
from CK and CK to QERR
from CK and CK to QERR
from CK and CK to Qn
from RESET to Qn
from RESET to PPO
from RESET to QERR
INACT(max)
Figure
Section
Section
Min
1
1
-
[1] [2]
[1] [2]
[1] [3]
[1]
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
2.
after RESET is taken LOW.
Min
450
1.41
0.5
1.2
1
-
-
-
-
SSTUH32866
11.1.
11.2.
Min
-
1
-
-
0.7
0.5
0.5
0.5
0.5
0.5
Typ
-
-
-
ACT(max)
Typ
-
-
-
-
-
-
-
-
-
Typ
-
-
-
-
-
-
-
-
-
-
after RESET is taken
Max
4
4
1
Max
-
1.8
1.8
3
2.4
2.0
3
3
3
Max
450
-
10
15
-
-
-
-
-
-
Unit
V/ns
V/ns
V/ns
13 of 28
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns