SSTUH32866EC/G,557 NXP Semiconductors, SSTUH32866EC/G,557 Datasheet - Page 17

• Manufacturer Part Number: SSTUH32866EC/G,557
• Description: IC BUFFER 1.8V 25BIT SOT536-1
• Manufacturer: NXP Semiconductors

Specifications of SSTUH32866EC/G,557

• Logic Type: 1:1, 1:2 Configurable Registered Buffer with Parity
• Supply Voltage: 1.7 V ~ 1.9 V
• Number Of Bits: 25, 14
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 96-LFBGA
• Logic Family: SSTU
• Logical Function: Registered Buffer
• Number Of Elements: 1
• Number Of Inputs: 25
• Number Of Outputs: 25
• High Level Output Current: -12mA
• Low Level Output Current: 12mA
• Package Type: LFBGA
• Propagation Delay Time: 3ns
• Operating Supply Voltage (typ): 1.8V
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Clock-edge Trigger Type: Posit/Negat-Edge
• Polarity: Non-Inverting
• Technology: CMOS
• Frequency (max): 450(Min)MHz
• Mounting: Surface Mount
• Pin Count: 96
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935277966557; SSTUH32866EC/G; SSTUH32866EC/G

Philips Semiconductors
11. Test information
9397 750 14199
Product data sheet
11.1 Parameter measurement information for data output load circuit
V
All input pulses are supplied by generators having the following characteristics:
PRR
The outputs are measured one at a time with one transition per measurement.
Fig 10. Load circuit, data output measurements
Fig 11. Voltage and current waveforms; inputs active and inactive times
Fig 12. Voltage waveforms; pulse duration
DD
= 1.8 V
(1) C
(1) I
CK inputs
10 MHz; Z
V
V
V
DD
ID
IH
IL
L
includes probe and jig capacitance.
= V
tested with clock and data inputs held at V
= 600 mV
= V
ref
0.1 V.
ref
+ 250 mV (AC voltage levels) for differential inputs. V
R
test point
test point
0
L
250 mV (AC voltage levels) for differential inputs. V
RESET
= 100
= 50 ; input slew rate = 1 V/ns
input
LVCMOS
1.8 V high-drive DDR2 configurable registered buffer with parity
T
L
= 50
Rev. 01 — 13 May 2005
I
DD
(1)
V
DD
t
INACT
/2
V
10 %
ICR
CK
CK
DUT
OUT
t
W
DD
or GND, and I
T
20 %, unless otherwise specified.
L
= 350 ps, 50
V
DD
V
ICR
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
t
IL
/2
IH
ACT
O
= GND for LVCMOS inputs.
= 0 mA.
= V
C
SSTUH32866
L
002aaa373
0 V
V
= 45 pF
DD
DD
002aaa372
V
ID
for LVCMOS inputs.
90 %
V
V
(1)
IH
IL
V
DD
002aab113
R
R
L
L
= 1000
= 1000
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