SSTUM32865ET/S,518 NXP Semiconductors, SSTUM32865ET/S,518 Datasheet - Page 12

• Manufacturer Part Number: SSTUM32865ET/S,518
• Description: IC BUFFER 1.8V 28BIT 160-TFBGA
• Manufacturer: NXP Semiconductors

Specifications of SSTUM32865ET/S,518

• Logic Type: 1:2 Registered Buffer with Parity
• Supply Voltage: 1.7 V ~ 2 V
• Number Of Bits: 28
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 160-TFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935284905518; SSTUM32865ET/S-T; SSTUM32865ET/S-T

PLL clock buffers
12
PCK2509SA
PCK2509SL
PCK2510SA
PCK2510SL
PCK2057
PCK857
PCK953
PCK2059B
PCK2159B
PCKV857
PCKV857A
PCKVF2057
PCKVF857
PCKU877
PCKU878
Memory interfaces
3.3
3.3
3.3
3.3
2.5
2.5;
3.3
3.3
2.5
2.5
2.5
2.5
2.5
2.5
1.8
1.8
50 to 150
50 to 150
50 to 150
50 to 150
70 to 190
66 to 167
50 to 125
100 to 185 SSTL-2
100 to 225 SSTL-2
60 to 190
100 to 250 SSTL-2
60 to 225
60 to 225
125 to 270
125 to 270
LVTTL
LVTTL
LVTTL
LVTTL
SSTL-2
SSTL-2
Differential
PECL
SSTL-2
SSTL-2
SSTL-2
Differential
clock
Differential
clock
9 x LVTTL
9 x LVTTL
10 x LVTTL
10 x LVTTL
11 x SSTL-2
11 x SSTL-2
9 x LVCMOS
13 x SSTL-2
13 x SSTL-2
11 x SSTL-2
11 x SSTL-2
11 x SSTL-2
11 x SSTL-2
11 x
differential
11 x
differential
80
80
80
80
75
100
55
75
75
100
75
35
35
40
40
200
200
200
200
75
100
100
75
75
100
75
75
75
40
40
125
125
125
125
270
150
60
75
75
150
50
50
50
50
50
Pin
select
Pin
select
Pin
select
Pin
select
I2C
-
Pin
select
I2C
I2C
-
-
I2C
Pin
select
Pin
select
Pin
select
0 to +70
0 to +70
0 to +70
0 to +70
0 to +70
0 to +85 output enable
0 to +70
0 to +70
0 to +70
0 to +70
0 to +70
0 to +70
0 to +70
0 to +70
0 to +70
bank output
enable, feedback
always enabled,
bypass
bank output
enable, bypass,
low-power mode
output enable,
feedback always
enabled, bypass
output enable,
bypass, low-
power mode
individual output
disable, bypass
output disable,
bypass, 1:18
effective fan-out
individual output
disable, bypass
individual output
disable, bypass
power-down;
input frequency
detection
power-down;
input frequency
detection
individual output
disable, bypass
power-down;
input frequency
detection
power-down;
selective disable,
bypass
power-down;
selective disable,
bypass, fast lock
time
TSSOP-24
TSSOP-24
TSSOP-24
TSSOP-24
TSSOP-48
TSSOP-48
LQFP-32
TFBGA-72
TFBGA-72
TSSOP-48,
TVSOP-48,
VFBGA-56
TSSOP-48,
TVSOP-48,
VFBGA-56
TSSOP-48
TSSOP-48,
TVSOP-48,
VFBGA-56
VFBGA-52,
HVQFN-40
VFBGA-52,
HVQFN-40
PC100/PC133 zero-delay
SDRAM clock distribution
(JEDEC compliant DIMMs)
PC100/PC133 zero-delay
SDRAM clock distribution
PC100/PC133 zero-delay
SDRAM clock distribution
(JEDEC compliant DIMMs)
PC100/PC133 zero-delay
SDRAM clock distribution
DDR zero-delay clock
distribution
DDR zero-delay clock
distribution, DIMMs
High-performance clock tree
design, NG-DIMMs
DDR200 - DDR333 zero-delay
clock distribution, DIMMs
DDR200 - DDR400 zero-delay
clock distribution, DIMMs
DDR200 - DDR266 zero-delay
clock distribution, DIMMs
DDR200 - DDR333 zero-delay
clock distribution, DIMMs
DDR200 - DDR400 zero-delay
clock distribution
DDR200 - DDR400 zero-delay
clock distribution, DIMMs
DDR2 400 - 533 zero delay
clock distribution, DIMMs
DDR2 400 - 533 zero delay
clock distribution, DIMMs