SSTUM32865ET/S,518 NXP Semiconductors, SSTUM32865ET/S,518 Datasheet - Page 6

• Manufacturer Part Number: SSTUM32865ET/S,518
• Description: IC BUFFER 1.8V 28BIT 160-TFBGA
• Manufacturer: NXP Semiconductors

Specifications of SSTUM32865ET/S,518

• Logic Type: 1:2 Registered Buffer with Parity
• Supply Voltage: 1.7 V ~ 2 V
• Number Of Bits: 28
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 160-TFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935284905518; SSTUM32865ET/S-T; SSTUM32865ET/S-T

NXP memory-interface solutions

Memory interfaces
feedback in
Differential
Differential
clock in
Power
down
Reset
V REF
CK
CK
D1
51
48
49
35
45
DDR PLL
To other channels
DDR register
PLL
1D
C1
R
N+1
N
1
SW00750
16 Q1A
32
Q1B
Differential
clock out 1
Differential
cock out N
Differential
feedback out
DDR 200 - 266
DDR (Double Data Rate) memory, the most common memory
standard shipping today, uses a clocking technique whereby
two data bits are transferred per clock cycle, or once every
clock edge, to significantly improve speed. Registers and
PLLs are used in the Registered DIMMs commonly used in
servers and other high-capacity systems, which require high
signal integrity independent of the load (that is, the number
of DIMMs occupying a slot on a memory bus). DDR memory
uses SSTL-2 (stub-series terminated logic, 2.5 V) signaling, with
pseudo-differential signaling for the address bus (a reference
voltage provides a precise threshold), and, to minimize timing
uncertainty, fully differential signaling for the clock signals.
low PLL jitter, and fast register propagation delay times
increasingly critical. NXP DDR registers and PLLs are designed
with special attention to these essential parameters,
so different device speeds incrementally meet the tighter
timing specifications associated with each DIMM speed grade
– in this case, 200 MT/s at a 100-MHz clock, and 266 MT/s at
a 133-MHz clock. Typical application of these devices is on
DDR DIMMs, but the PCK2057 integrates an I
enable control and is typically used on the motherboard.
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The higher speed of DDR memory makes signal integrity,
PCKV857
PCKV857A
PCK2057
SSTV16857
SSTV16859
2.5-V typical supply voltage
SSTL_2 (Stub Series Terminated Logic, 2.5-V) signaling
Double Data Rate (DDR)
200- to 266-MT/s data rates
100- to 133-MHz clock rates
70- to 190-MHz differential 1:10 clock driver
100- to 250-MHz differential 1:10 clock driver
70- to 190-MHz differential 1:10 clock driver with
I
14-bit SSTL_2 registered driver with differential
clock inputs
13-bit 1:2 SSTL_2 registered driver with differential
clock inputs for stacked DDR DIMMs
2
C control
2
C port for output-