ADC1213D080HN-C1 IDT, ADC1213D080HN-C1 Datasheet - Page 30

• Manufacturer Part Number: ADC1213D080HN-C1
• Description: Analog to Digital Converters - ADC
• Manufacturer: IDT

Specifications of ADC1213D080HN-C1

• Rohs: yes

Integrated Device Technology
Table 28.
Default values are highlighted.
Table 29.
[1]
ADC1213D_SER 8
Product data sheet
Bit
7 to 4 -
3 to 0 CFG_SETUP[3:0]
CFG_SETUP[3:0] ADC A ADC B Lane 0 Lane 1 F
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
F: Octets per frame clock cycle
HD: High-density mode
K: Frame per multi-frame
M: Converters per device
L: Lane per converter device
CS: Number of control bits per conversion sample
CF: Control words per frame clock cycle and link
S: Number of samples transmitted per single converter per frame cycle
Symbol
1010
1100
1101
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1011
1110
1111
Ser_Cfg_Setup (address 0803h)
JESD204A configuration table
OFF
OFF
OFF
OFF
ON
ON
ON
ON
ON
ON
ON
OFF
OFF
OFF
OFF
ON
ON
ON
ON
ON
ON
ON
Access Value
-
R/W
OFF
OFF
OFF
OFF
ON
ON
ON
ON
ON
ON
ON
0000
OFF
OFF
OFF
OFF
ON
ON
ON
ON
ON
ON
ON
Rev. 08 — 2 July 2012
Description
not used
quick configuration of JESD204A. These settings overrule the
CFG_PAD configuration (see Table 29).
2
4
4
1
1
2
2
2
2
2
2
[1]
HD
0
0
0
1
1
0
0
0
0
0
0
[1]
reserved
reserved
reserved
reserved
reserved
K
17
17
9
5
5
9
9
9
9
9
9
[1]
Dual 12-bit ADC; serial JESD204A interface
M
2
2
2
1
1
1
1
1
1
2
2
[1]
L
ADC1213D series
2
1
1
2
2
1
1
1
1
2
2
[1]
power-down
(F  K)  17
(F  K)  17
(F  K)  17
(F  K)  17
(F  K)  17
(F  K)  17
(F  K)  17
(F  K)  17
(F  K)  17
Comment
alignment
test: loop
chip
CS
© IDT 2012. All rights reserved.
1
1
1
1
1
1
1
1
1
1
1
[1]
CF
0
0
0
0
0
0
0
0
0
0
0
[1]
30 of 40
S
1
1
1
1
1
1
1
1
1
1
1
[1]