MAX11624EEG+T Maxim Integrated, MAX11624EEG+T Datasheet - Page 10

• Manufacturer Part Number: MAX11624EEG+T
• Description: Analog to Digital Converters - ADC 10-Bit 16Ch 300ksps 5V Precision ADC
• Manufacturer: Maxim Integrated

Specifications of MAX11624EEG+T

• Rohs: yes
• Number Of Channels: 16
• Architecture: SAR
• Conversion Rate: 300 KSPs
• Resolution: 10 bit
• Input Type: Single-Ended
• Interface Type: 3-Wire (SPI, Microwire), QSPI
• Operating Supply Voltage: 4.75 V to 5.25 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Maximum Power Dissipation: 762 mW
• Minimum Operating Temperature: - 40 C
• Number Of Converters: 1
• Voltage Reference: 4.096 V

10-Bit, 300ksps ADCs
with FIFO and Internal Reference
10
(4 CHANNELS)
MAX11618
MAX11619
______________________________________________________________________________________
5, 6, 7
1–4
10
11
12
13
14
15
16
—
—
—
—
8
9
(8 CHANNELS)
MAX11620
MAX11621
() MAX11618/MAX11619 ONLY
TOP VIEW
1–7
PIN
10
11
12
13
14
15
16
—
—
—
—
—
8
9
AIN7/(CNVST)
AIN4 (N.C.)
AIN5 (N.C.)
AIN6 (N.C.)
AIN0
AIN1
AIN2
AIN3
1
2
3
4
5
6
7
8
(16 CHANNELS)
+
MAX11624
MAX11625
MAX11618–
MAX11621
QSOP
1–15
—
16
17
18
19
20
21
22
23
24
—
—
—
—
16
15
14
13
12
11
10
9
EOC
DOUT
DIN
SCLK
CS
V
GND
REF
DD
CNVST/AIN15
CNVST/AIN7
AIN0–AIN14
AIN0–AIN3
AIN0–AIN6
CNVST
NAME
DOUT
SCLK
GND
EOC
N.C.
REF
V
DIN
CS
DD
Analog Inputs
No Connection. Not internally connected.
Analog Inputs
Analog Inputs
Active-Low Conversion Start Input/Analog Input 15. See
Table 3 for details on programming the setup register.
Active-Low Conversion Start Input/Analog Input 7. See Table
3 for details on programming the setup register.
Active-Low Conversion Start Input. See Table 3 for details on
programming the setup register.
Reference Input. Bypass to GND with a 0.1µF capacitor.
Ground
Power Input. Bypass to GND with a 0.1µF capacitor.
Active-Low Chip-Select Input. When CS is low, the serial
interface is enabled. When CS is high, DOUT is high
impedance.
Serial Clock Input. Clocks data in and out of the serial
interface (duty cycle must be 40% to 60%). See Table 3 for
details on programming the clock mode.
Serial Data Input. DIN data is latched into the serial interface
on the rising edge of SCLK.
S er i al D ata Outp ut. D ata i s cl ocked out on the fal l i ng ed g e of
S C LK. H i g h i m p ed ance w hen CS i s connected to V
End of Conversion Output. Data is valid after EOC pulls low.
AIN10
AIN11
AIN0
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
AIN8
AIN9
10
11
12
1
2
3
4
5
6
7
8
9
+
MAX11624–
MAX11625
QSOP
FUNCTION
Pin Configurations
24
23
22
21
20
19
18
17
16
15
14
13
EOC
DOUT
DIN
SCLK
CS
V
GND
REF
CNVST/AIN15
AIN14
AIN13
AIN12
DD
Pin Description
D D
.