MAX11624EEG+T Maxim Integrated, MAX11624EEG+T Datasheet - Page 18

• Manufacturer Part Number: MAX11624EEG+T
• Description: Analog to Digital Converters - ADC 10-Bit 16Ch 300ksps 5V Precision ADC
• Manufacturer: Maxim Integrated

Specifications of MAX11624EEG+T

• Rohs: yes
• Number Of Channels: 16
• Architecture: SAR
• Conversion Rate: 300 KSPs
• Resolution: 10 bit
• Input Type: Single-Ended
• Interface Type: 3-Wire (SPI, Microwire), QSPI
• Operating Supply Voltage: 4.75 V to 5.25 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Maximum Power Dissipation: 762 mW
• Minimum Operating Temperature: - 40 C
• Number Of Converters: 1
• Voltage Reference: 4.096 V

10-Bit, 300ksps ADCs
with FIFO and Internal Reference
In clock mode 10, the wake-up, acquisition, conversion,
and shutdown sequences are initiated by writing an
input data byte to the conversion register, and are per-
formed automatically using the internal oscillator. This
is the default clock mode upon power-up. See Figure 6
for clock mode 10 timing.
Initiate a scan by writing a byte to the conversion regis-
ter. The MAX11618–MAX11621/MAX11624/MAX11625
then power up, scan all requested channels, store the
results in the FIFO, and shut down. After the scan is
18
Figure 5. Clock Mode 01
Figure 6. Clock Mode 10
DIN
SCLK
DOUT
EOC
CS
CNVST
SCLK
DOUT
EOC
CS
THE CONVERSION BYTE BEGINS THE ACQUISITION. CNVST IS NOT REQUIRED.
______________________________________________________________________________________
(ACQUISITION1)
Conversions Using the Serial Interface
REQUEST MULTIPLE CONVERSIONS BY SETTING CNVST LOW FOR EACH CONVERSION.
(CONVERSION1)
Performing Conversions in Clock Mode 10
Internally Timed Acquisitions and
(ACQUISITION2)
(CONVERSION BYTE)
(CONVERSION2)
(UP TO 514 INTERNALLY CLOCKED ACQUISITIONS AND CONVERSIONS)
MSB1
MSB1
complete, EOC is pulled low and the results are avail-
able in the FIFO. EOC stays low until CS is pulled low
again.
In clock mode 11, acquisitions and conversions are ini-
tiated by writing to the conversion register and are per-
formed one at a time using the SCLK as the conversion
clock. Scanning and averaging are disabled, and the
conversion result is available at DOUT during the con-
version. See Figure 7 for clock mode 11 timing.
Conversions Using the Serial Interface
LSB1
Externally Clocked Acquisitions and
Performing Conversions in Clock Mode 11
LSB1
MSB2
MSB2