MAX11624EEG+T Maxim Integrated, MAX11624EEG+T Datasheet - Page 12

• Manufacturer Part Number: MAX11624EEG+T
• Description: Analog to Digital Converters - ADC 10-Bit 16Ch 300ksps 5V Precision ADC
• Manufacturer: Maxim Integrated

Specifications of MAX11624EEG+T

• Rohs: yes
• Number Of Channels: 16
• Architecture: SAR
• Conversion Rate: 300 KSPs
• Resolution: 10 bit
• Input Type: Single-Ended
• Interface Type: 3-Wire (SPI, Microwire), QSPI
• Operating Supply Voltage: 4.75 V to 5.25 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Maximum Power Dissipation: 762 mW
• Minimum Operating Temperature: - 40 C
• Number Of Converters: 1
• Voltage Reference: 4.096 V

10-Bit, 300ksps ADCs
with FIFO and Internal Reference
The MAX11618–MAX11621/MAX11624/MAX11625
ADCs use a successive-approximation register (SAR)
conversion technique and an on-chip T/H block to con-
vert voltage signals into a 10-bit digital result. This single-
ended configuration supports unipolar signal ranges.
The ADC’s input-tracking circuitry has a 1MHz small-
signal bandwidth, so it is possible to digitize high-speed
transient events and measure periodic signals with
bandwidths exceeding the ADC’s sampling rate by
using undersampling techniques. Anti-alias prefiltering
of the input signals is necessary to avoid high-frequency
signals aliasing into the frequency band of interest.
Internal ESD protection diodes clamp all pins to V
and GND, allowing the inputs to swing from (GND -
0.3V) to (V
accurate conversions near full scale, the inputs must
not exceed V
GND by 50mV. If an off-channel analog input voltage
exceeds the supplies, limit the input current to 2mA.
The MAX11618–MAX11621/MAX11624/MAX11625 fea-
ture a serial interface compatible with SPI/QSPI and
MICROWIRE devices. For SPI/QSPI, ensure the CPU
serial interface runs in master mode so it generates the
serial clock signal. Select the SCLK frequency of 10MHz
or less, and set clock polarity (CPOL) and phase
(CPHA) in the µP control registers to the same value.
The MAX11618–MAX11621/MAX11624/MAX11625
operate with SCLK idling high or low, and thus operate
with CPOL = CPHA = 0 or CPOL = CPHA = 1. Set CS
low to latch input data at DIN on the rising edge of
SCLK. Output data at DOUT is updated on the falling
edge of SCLK. Results are output in binary format.
Serial communication always begins with an 8-bit input
data byte (MSB first) loaded from DIN. A high-to-low
transition on CS initiates the data input operation. The
input data byte and the subsequent data bytes are
clocked from DIN into the serial interface on the rising
edge of SCLK. Tables 1–5 detail the register descrip-
tions. Bits 5 and 4, CKSEL1 and CKSEL0, respectively,
control the clock modes in the setup register (see Table
3). Choose between four different clock modes for vari-
ous ways to start a conversion and determine whether
the acquisitions are internally or externally timed. Select
clock mode 00 to configure CNVST/AIN_ to act as a
conversion start and use it to request the programmed,
internally timed conversions without tying up the serial
bus. In clock mode 01, use CNVST to request
12
______________________________________________________________________________________
DD
DD
+ 0.3V) without damage. However, for
by more than 50mV or be lower than
Analog Input Protection
3-Wire Serial Interface
Converter Operation
Input Bandwidth
DD
Figure 3. Equivalent Input Circuit
conversions one channel at a time, controlling the sam-
pling speed without tying up the serial bus. Request
and start internally timed conversions through the serial
interface by writing to the conversion register in the
default clock mode 10. Use clock mode 11 with SCLK
up to 4.8MHz for externally timed acquisitions to
achieve sampling rates up to 300ksps. Clock mode 11
disables scanning and averaging. See Figures 4–7 for
timing specifications and how to begin a conversion.
These devices feature an active-low, end-of-conversion
output. EOC goes low when the ADC completes the last
requested operation and is waiting for the next input
data byte (for clock modes 00 and 10). In clock mode
01, EOC goes low after the ADC completes each
requested operation. EOC goes high when CS or
CNVST goes low. EOC is always high in clock mode 11.
The single-ended analog input conversion modes can
be configured by writing to the setup register (see
Table 3). Single-ended conversions are internally refer-
enced to GND (see Figure 3).
AIN0–AIN3 are available on the MAX11618–MAX11621/
MAX11624/MAX11625. AIN4–AIN7 are only available on
the MAX11620–MAX11625. AIN8–AIN15 are only available
on the MAX11624/MAX11625. See Tables 2–5 for more
details on configuring the inputs. For the inputs that can be
configured as CNVST or an analog input, only one can be
used at a time.
The MAX11618–MAX11621/MAX11624/MAX11625
always operate in unipolar mode. The analog inputs are
internally referenced to GND with a full-scale input
range from 0 to V
AIN0–AIN15
GND
HOLD
REF
.
GND
REF
V
HOLD
CIN+
CIN-
DD
/2
Single-Ended Inputs
DAC
COMPARATOR
HOLD
Unipolar
+
-