MAXQ8913X-0000+ Maxim Integrated, MAXQ8913X-0000+ Datasheet - Page 10

• Manufacturer Part Number: MAXQ8913X-0000+
• Description: 16-bit Microcontrollers - MCU 16-Bit Mxd Sgnl MCU w/Op Amp ADC & DAC
• Manufacturer: Maxim Integrated

Specifications of MAXQ8913X-0000+

• Rohs: yes
• Core: RISC
• Processor Series: MAXQ8913
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 20 MHz
• Program Memory Size: 64 KB
• Data Ram Size: 4 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 2.7 V to 3.6 V
• Package / Case: WLP-58
• Mounting Style: SMD/SMT
• A/d Bit Size: 12 bit
• A/d Channels Available: 7
• Interface Type: I2C, SPI, USART
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 12
• Number Of Timers: 1
• Program Memory Type: Flash
• Part # Aliases: 90-08913+D02

16-Bit, Mixed-Signal Microcontroller with Op Amps,
ADC, and DACs for All-in-One Servo Loop Control
I
(All values referenced to V
Note 20: A device must internally provide a hold time of at least 300ns for the SDA signal (referenced to the V
Note 21: The maximum t
Note 22: A fast-mode I
Note 23: C
10
2
Operating Frequency
Hold Time After (Repeated) START
Clock Low Period
Clock High Period
Setup Time for Repeated START
Hold Time for Data (Notes 20, 21)
Setup Time for Data (Note 22)
SDA/SCL Fall Time (Note 23)
SDA/SCL Rise Time (Note 23)
Setup Time for STOP
Bus-Free Time Between STOP and START
Capacitive Load for Each Bus Line
Noise Margin at the Low Level for Each Connected
Device (Including Hysteresis)
Noise Margin at the High Level for Each Connected
Device (Including Hysteresis)
C BUS CONTROLLER TIMING
______________________________________________________________________________________
signal) to bridge the undefined region of the falling edge of SCL.
be met. This is automatically the case if the device does not stretch the low period of the SCL signal. If such a device does
stretch the low period of the SCL signal, it must output the next data bit to the SDA line t
= 1250ns (according to the standard-mode I
B
= Total capacitance of one bus line in pF.
PARAMETER
2
C-bus device can be used in a standard-mode I
HD:DAT
IH_I2C(MIN)
need only be met if the device does not stretch the low period (t
and V
IL_I2C(MAX)
. See Figure 5.)
2
C specification) before the SCL line is released.
SYMBOL
t
t
HIGH_I2C
V
t
LOW_I2C
t
t
t
t
V
HD:STA
HD:DAT
SU:STO
SU:STA
SU:DAT
t
t
NH_I2C
R_I2C
NL_I2C
F_I2C
t
f
BUF
C
I2C
B
V
V
STANDARD MODE
0.1 x
0.2 x
2
MIN
250
DVDD
DVDD
4.0
4.7
4.0
4.7
4.0
4.7
C-bus system, but the requirement t
0
0
MAX
1000
3.45
100
300
400
20 + 0.1C
20 + 0.1C
LOW_I2C
R_I2C(MAX)
V
V
0.1 x
0.2 x
MIN
100
DVDD
DVDD
0.6
1.3
0.6
0.6
0.6
1.3
0
0
FAST MODE
) of the SCL signal.
B
B
+ t
SU:DAT
IH_I2C(MIN)
SU:DAT
MAX
400
300
300
400
0.9
≥ 250ns must
= 1000 + 250
of the SCL
UNITS
kHz
μs
μs
μs
μs
μs
ns
ns
ns
μs
μs
pF
V
V