MAXQ8913X-0000+ Maxim Integrated, MAXQ8913X-0000+ Datasheet - Page 19

• Manufacturer Part Number: MAXQ8913X-0000+
• Description: 16-bit Microcontrollers - MCU 16-Bit Mxd Sgnl MCU w/Op Amp ADC & DAC
• Manufacturer: Maxim Integrated

Specifications of MAXQ8913X-0000+

• Rohs: yes
• Core: RISC
• Processor Series: MAXQ8913
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 20 MHz
• Program Memory Size: 64 KB
• Data Ram Size: 4 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 2.7 V to 3.6 V
• Package / Case: WLP-58
• Mounting Style: SMD/SMT
• A/d Bit Size: 12 bit
• A/d Channels Available: 7
• Interface Type: I2C, SPI, USART
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 12
• Number Of Timers: 1
• Program Memory Type: Flash
• Part # Aliases: 90-08913+D02

divided into two major types: system registers and
peripheral registers. The common register set, also
known as the system registers, includes the ALU, accu-
mulator registers, data pointers, interrupt vectors and
control, and stack pointer. The peripheral registers
define additional functionality that could be included by
different products based on the MAXQ architecture.
This functionality is broken up into discrete modules so
that only the features required for a given product need
to be included.
The module and register functions are covered fully in
the MAXQ Family User’s Guide and the MAXQ Family
User’s Guide: MAXQ8913 Supplement . This information
includes the locations of status and control bits and a
detailed description of their function and reset values.
Refer to this documentation for a complete understand-
ing of the features and operation of the microcontroller.
The microcontroller incorporates one instance of the
16-bit programmable timer/counter B peripheral. It can
be used in counter/timer/capture/compare/PWM func-
tions, allowing precise control of internal and external
events. The timer/counter supports clock input prescal-
ing and set/reset/toggle PWM/output control functionali-
ty not found on other MAXQ timer implementations. A
new register, TBC, supports PWM/output control func-
tions. A distinguishing characteristic of timer/counter B
is that its count ranges from 0000h to the value stored
in the 16-bit capture/reload register (TBR) counting up.
The timer/counter B timer is fully described in the
MAXQ Family User’s Guide: MAXQ8913 Supplement .
Timer B operational modes include the following:
• Autoreload
• Autoreload using external pin
• Capture using external pin
• Up/down count using external pin
• Up-count PWM/output
• Up/down PWM/output
• Clock output on TBxB pin
• Up/down PWM mode with double-buffered output
• On interrupt, the user loads buffered output data,
16-Bit, Mixed-Signal Microcontroller with Op Amps,
mode:
which does not begin sending until current iteration
is completed. This enables a glitchless PWM
because there is no output pause while interrupt is
being serviced, and a race condition does not occur
in setting TBC before it is used. A TBC value written
ADC, and DACs for All-in-One Servo Loop Control
______________________________________________________________________________________
Programmable Timer
An internal watchdog timer greatly increases system
reliability. The timer resets the device if software execu-
tion is disturbed. The watchdog timer is a free-running
counter designed to be periodically reset by the appli-
cation software. If software is operating correctly, the
counter is periodically reset and never reaches its max-
imum count. However, if software operation is interrupt-
ed, the timer does not reset, triggering a system reset
and optionally a watchdog timer interrupt. This protects
the system against electrical noise or electrostatic dis-
charge (ESD) upsets that could cause uncontrolled
processor operation. The internal watchdog timer is an
upgrade to older designs with external watchdog
devices, reducing system cost and simultaneously
increasing reliability.
The watchdog timer is controlled through bits in the
WDCN register. Its timeout period can be set to one of
four programmable intervals ranging from 2
system clocks in its default mode, allowing flexibility to
support different types of applications. The interrupt
occurs 512 system clocks before the reset, allowing the
system to execute an interrupt and place the system in
a known, safe state before the device performs a total
system reset. At 10MHz, watchdog timeout periods can
be programmed from 410µs to 54s, depending on the
system clock mode.
The MAXQ8913 contains four uncommitted op amps. It
is electrically acceptable for op-amp outputs to exceed
the reference voltage, but they saturate the ADC code.
Gains and offsets introduced in the op-amp circuits
should be carefully set to maintain the outputs of the op
amps at or below the reference voltage if the ADC con-
verted values are expected to be unsaturated. The
device provides REFA as an output to aid in this
endeavor.
The outputs of the op amps are internally connected to
ADC channels 2 to 5. Unused op amps should be con-
nected with their “+” input terminal grounded and the
output and “-” input terminals shorted together.
The power stage of the MAXQ8913 is designed to drive
a stereo Class D amplifier (DAMP). These amplifiers are
after timer rollover becomes effective during the fol-
lowing counter cycle.
Class D Amplifier Output Stage
Differential DAC and External
Watchdog Timer
Operation
Op Amps
12
to 2
19
21