MAXQ8913X-0000+ Maxim Integrated, MAXQ8913X-0000+ Datasheet - Page 20

• Manufacturer Part Number: MAXQ8913X-0000+
• Description: 16-bit Microcontrollers - MCU 16-Bit Mxd Sgnl MCU w/Op Amp ADC & DAC
• Manufacturer: Maxim Integrated

Specifications of MAXQ8913X-0000+

• Rohs: yes
• Core: RISC
• Processor Series: MAXQ8913
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 20 MHz
• Program Memory Size: 64 KB
• Data Ram Size: 4 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 2.7 V to 3.6 V
• Package / Case: WLP-58
• Mounting Style: SMD/SMT
• A/d Bit Size: 12 bit
• A/d Channels Available: 7
• Interface Type: I2C, SPI, USART
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 12
• Number Of Timers: 1
• Program Memory Type: Flash
• Part # Aliases: 90-08913+D02

16-Bit, Mixed-Signal Microcontroller with Op Amps,
ADC, and DACs for All-in-One Servo Loop Control
suitable for driving self-commutating DC motors or
voice coil motors.
Each external DAMP is differentially driven by a 10-bit
DAC. The DAC output common mode is 1.25V, based
on the bandgap reference, and each differential output
can swing from GND to 2.5V (if V
effective differential peak-to-peak voltage is 5V. The
DAMP has a 6dB gain, so its ouput can swing 10V (if
DAMP supply = 5V).
The differential output voltage follows the simple formula:
There are four Class D amplifier control bits and one
status bit. The SHDNR and SHDNL pins are the active-
high shutdown controls for the two Class D amplifiers,
respectively. The SYNCIN_DIV bits control the input
clock to the Class D amplifier sawtooth generator. The
SYNCIN frequency must fall within 2MHz and 2.8MHz.
The optimal frequency is 2.2MHz. The frequency of the
high-frequency oscillator and the divide ratio need to
be chosen wisely to accomodate this requirement. For
example, if a 9MHz crystal is used, a divide-by-4 ratio
produces a SYNCIN frequency of 2.25MHz.
Table 1 shows the divide ratio applied to the high-fre-
quency oscillator output based on the value of
SYNCIN_DIV.
Table 1. SYNCIN Divisor vs. SYNCIN_DIV
Value
To start operating the DACs and DAMPs, the following
procedural steps should be followed:
1) Set both DAC inputs to code 512.
2) Enable the SYNCIN clock by setting an appropriate
3) Wait 100µs. Clear the SHDNR and SHDNL bits.
4) Wait 100µs.
One or both DAMPs can be shut down at any time by
setting the corresponding SHDN bit. If both DAMPs are
shut down, the firmware should disable the SYNCIN
signal.
20
value for SYNCIN_DIV.
______________________________________________________________________________________
SYNCIN_DIV
0 (default)
V
DIFF
1
2
3
= 2.5 x (code - 512)/512V
SYNCIN clock off
HF DIVIDED BY
DVDD
2
3
4
≥ 3V), so the
The DAMP FAULT bit goes high for at least 500ns fol-
lowing a thermal shutdown or current-limit event. It
stays low in shutdown and is glitch-free during power-
up. FAULT interrupts the microcontroller if enabled.
Alternatively, the firmware can poll the bit periodically to
detect faults of the type previously described.
While the MAXQ8913 contains power drivers for the
actuator, the positive terminal of each differential DAC
output pair is buffered and available as an output pin.
This feature is intended primarily for test, and no signifi-
cant load should be added to the DAC1 and DAC2
pins. The specifications for these pins are not yet deter-
mined, except for the no-load output voltage, which is
expected to be between GND and 2.5V.
DAC3 and DAC4 are single-ended DACs. Their outputs
are intended for driving the positive terminal (through a
resistor) of single-supply op amps to force the virtual
GND to a value that allows the op amp to operate
below and above the virtual ground DC value.
Operated in this fashion, the DACs can also serve as
offset cancellation devices as necessary.
Popular optical-image stabilization implementations
include the use of Hall-effect elements for position feed-
back. Hall-effect elements require a current to flow
through two of its terminals for proper operation. The
device includes two current sinks intended to drive
these elements. The current sinks are programmable
between 0 and 15.94mA with 62.5mA resolution
through an 8-bit code. Code 0 turns them off.
When operating Hall-effect elements from 3V, the maxi-
mum achievable current is given by (3V - 0.5V)/R
where 0.5V is the minimum voltage value at the input of
the current sink. For example, if R
maximum current is 10mA.
If higher currents are desirable, the user must provide a
larger supply voltage to the Hall-effect element. In this
case, care must be exercised so that the output nodes
of the Hall-effect element do not exceed V
Exceeding V
diodes of the op-amp terminals to begin conduction
and waste power when the device is in sleep mode. If
supplying a voltage larger than V
element, a switchable supply is recommended to avoid
the leakage path identified above.
AVDD
DAC1 and DAC2 Buffers
could cause the input-protection
SINK1 and SINK2
DAC3 and DAC4
AVDD
HALL
to the Hall-effect
= 250Ω, the
AVDD
HALL
,
.