MAXQ8913X-0000+ Maxim Integrated, MAXQ8913X-0000+ Datasheet - Page 17

• Manufacturer Part Number: MAXQ8913X-0000+
• Description: 16-bit Microcontrollers - MCU 16-Bit Mxd Sgnl MCU w/Op Amp ADC & DAC
• Manufacturer: Maxim Integrated

Specifications of MAXQ8913X-0000+

• Rohs: yes
• Core: RISC
• Processor Series: MAXQ8913
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 20 MHz
• Program Memory Size: 64 KB
• Data Ram Size: 4 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 2.7 V to 3.6 V
• Package / Case: WLP-58
• Mounting Style: SMD/SMT
• A/d Bit Size: 12 bit
• A/d Channels Available: 7
• Interface Type: I2C, SPI, USART
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 12
• Number Of Timers: 1
• Program Memory Type: Flash
• Part # Aliases: 90-08913+D02

The following is an introduction to the primary features
of the microcontroller. More detailed descriptions of the
device features can be found in the data sheets, errata
sheets, and user’s guides described later in the
Additional Documentation section.
The MAXQ core is a low-cost, high-performance,
CMOS, fully static, 16-bit RISC microcontroller with
flash memory. The MAXQ8913 supports 7 channels of
high-performance measurement using a 10-bit succes-
sive approximation register (SAR) ADC with internal ref-
erence. These parts are structured on a highly
advanced, accumulator-based, 16-bit RISC architec-
ture. Fetch and execution operations are completed in
one cycle without pipelining because the instruction
contains both the op code and data. The result is a
streamlined microcontroller performing at up to 1 million
instructions per second (MIPS) for each MHz of the sys-
tem operating frequency.
The highly efficient core is supported by a 16-level
hardware stack, enabling fast subroutine calling and
task switching. Data can be quickly and efficiently
manipulated with three internal data pointers. Multiple
data pointers allow more than one function to access
data memory without having to save and restore data
pointers each time. The data pointers can automatically
increment or decrement following an operation, elimi-
nating the need for software intervention. As a result,
application speed is greatly increased.
The instruction set is composed of fixed-length, 16-bit
instructions that operate on registers and memory loca-
tions. The instruction set is highly orthogonal, allowing
arithmetic and logical operations to use any register
along with the accumulator. Special function registers
control the peripherals and are subdivided into register
modules. The family architecture is modular so new
devices and modules can reuse code developed for
existing products.
The architecture is transport triggered. This means that
writes or reads from certain register locations can also
cause side effects to occur. These side effects form the
basis for the higher level op codes defined by the
assembler, such as ADDC, OR, JUMP, etc. The op
codes are actually implemented as MOVE instructions
between certain register locations, while the assembler
handles the encoding, which need not be a concern to
the programmer.
16-Bit, Mixed-Signal Microcontroller with Op Amps,
ADC, and DACs for All-in-One Servo Loop Control
MAXQ Core Architecture
______________________________________________________________________________________
Detailed Description
Instruction Set
The 16-bit instruction word is designed for efficient exe-
cution. Bit 15 indicates the format for the source field of
the instruction. Bits 0 to 7 represent the source for the
transfer. Depending on the value of the format field, this
can be either an immediate value or a source register.
If this field represents a register, the lower 4 bits con-
tain the module specifier and the upper 4 bits contain
the register index in that module. Bits 8 to 14 represent
the destination for the transfer. This value always repre-
sents a destination register, with the lower 4 bits con-
taining the module specifier and the upper 3 bits
containing the register subindex within that module.
Any time that it is necessary to directly select one of the
upper 24 registers as a destination, the prefix register,
PFX, is needed to supply the extra destination bits. This
prefix register write is inserted automatically by the
assembler and requires only one additional execution
cycle.
The device incorporates several memory areas:
• 4KB utility ROM
• 64KB of flash memory for program storage
• 4KB of SRAM for storage of temporary variables
• 16-level stack memory for storage of program return
The incorporation of flash memory allows the devices to
be reprogrammed multiple times allowing modifications
to user applications post production. Additionally, the
flash can be used to store application information
including configuration data and log files.
The default memory organization is organized as a
Harvard architecture, with separate address spaces for
program and data memory. Pseudo-Von Neumann
memory organization is supported through the utility
ROM for applications that require dynamic program
modification and execution from RAM. The pseudo-Von
Neumann memory organization places the code, data
and utility ROM memories into a single contiguous
memory map.
A 16-bit-wide hardware stack provides storage for pro-
gram return addresses and can also be used as gener-
al-purpose data storage. The stack is used
automatically by the processor when the CALL, RET,
and RETI instructions are executed and when an inter-
rupt is serviced. An application can also store values in
the stack explicitly by using the PUSH, POP, and POPI
instructions.
addresses and general-purpose use
Memory Organization
Stack Memory
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