S9S12GA240F0MLL Freescale Semiconductor, S9S12GA240F0MLL Datasheet - Page 493
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S9S12GA240F0MLL
Manufacturer Part Number
S9S12GA240F0MLL
Description
16-bit Microcontrollers - MCU 16BIT 240KB FLASH
Manufacturer
Freescale Semiconductor
Datasheet
1.S9S12G96F0CLL.pdf
(1292 pages)
Specifications of S9S12GA240F0MLL
Rohs
yes
Core
S12
Processor Series
MC9S12G
Data Bus Width
16 bit
Maximum Clock Frequency
25 MHz
Program Memory Size
240 KB
Data Ram Size
4 KB
On-chip Adc
Yes
Operating Supply Voltage
3.13 V to 5.5 V
Operating Temperature Range
- 40 C to + 125 C
Package / Case
LQFP-100
Mounting Style
SMD/SMT
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
S9S12GA240F0MLL
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Chapter 14
Analog-to-Digital Converter (ADC12B12CV2)
Revision History
Freescale Semiconductor
Number
Version
V02.00
V02.01
V02.02
V02.03
V02.04
V02.05
V02.06
V02.07
V02.08
V02.09
V02.10
V02.11
13 May 2009
22. Jun 2012
30.Nov 2009
09 Feb 2010
26 Feb 2010
25 Aug 2010
09 Sep 2010
11 Feb 2011
29 Mar 2011
14 Apr 2010
29 Jun 2012
02 Oct 2012
Revision
Date
13 May 2009
22. Jun 2012
29. Jun 2012
30.Nov 2009
09 Feb 2010
26 Feb 2010
25 Aug 2010
09 Sep 2010
11 Feb 2011
29 Mar 2011
14 Apr 2010
02 Oct 2012
Effective
Date
MC9S12G Family Reference Manual, Rev.1.23
Author
Initial version copied from V01.06,
changed unused Bits in ATDDIEN to read logic 1
Updated
description of internal channels.
Updated register ATDDR (left/right justified result) description
in section
added table
Fixed typo in
resolution
Corrected
description of internal channels.
Corrected typos to be in-line with SoC level pin naming
conventions for VDDA, VSSA, VRL and VRH.
Removed feature of conversion during STOP and general
wording clean up done in
Description
Update of internal only information.
Connectivity Information regarding internal channel_6 added
to
Fixed typo in bit description field
CB, CA. Last sentence contained a wrong highest channel
number (it is not AN7 to AN0 instead it is AN11 to AN0).
Update of register write access information in section
14.3.2.9/14-514.
Removed IP name in block diagram
Added user information to avoid maybe false external trigger
events when enabling the external trigger mode
(Section 14.4.2.1, “External Trigger
Table
14-15.
Table 14-15
14.3.2.12.1/14-516
Table 14-15
Table 14-21
Table
Description of Changes
14-9- conversion result for 3mV and 10bit
Analog Input Channel Select Coding -
Analog Input Channel Select Coding -
to improve feature description.
Section 14.4, “Functional
and
Table 14-14
14.3.2.12.2/14-517
Input).
Figure 14-1
for bits CD, CC,
and
495
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