S9S12GA240F0MLL Freescale Semiconductor, S9S12GA240F0MLL Datasheet - Page 672
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S9S12GA240F0MLL
Manufacturer Part Number
S9S12GA240F0MLL
Description
16-bit Microcontrollers - MCU 16BIT 240KB FLASH
Manufacturer
Freescale Semiconductor
Datasheet
1.S9S12G96F0CLL.pdf
(1292 pages)
Specifications of S9S12GA240F0MLL
Rohs
yes
Core
S12
Processor Series
MC9S12G
Data Bus Width
16 bit
Maximum Clock Frequency
25 MHz
Program Memory Size
240 KB
Data Ram Size
4 KB
On-chip Adc
Yes
Operating Supply Voltage
3.13 V to 5.5 V
Operating Temperature Range
- 40 C to + 125 C
Package / Case
LQFP-100
Mounting Style
SMD/SMT
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
S9S12GA240F0MLL
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Serial Communication Interface (S12SCIV5)
20.3.2.3
Read: Anytime, if AMAP = 1
Write: Anytime, if AMAP = 1
20.3.2.4
Read: Anytime, if AMAP = 1
Write: Anytime, if AMAP = 1
674
Module Base + 0x0000
Module Base + 0x0001
RXEDGIF
BERRIF
BERRV
Reset
Reset
BKDIF
Field
7
2
1
0
W
W
R
R
RXEDGIF
RXEDGIE
Receive Input Active Edge Interrupt Flag — RXEDGIF is asserted, if an active edge (falling if RXPOL = 0,
rising if RXPOL = 1) on the RXD input occurs. RXEDGIF bit is cleared by writing a “1” to it.
0 No active receive on the receive input has occurred
1 An active edge on the receive input has occurred
Bit Error Value — BERRV reflects the state of the RXD input when the bit error detect circuitry is enabled and
a mismatch to the expected value happened. The value is only meaningful, if BERRIF = 1.
0 A low input was sampled, when a high was expected
1 A high input reassembled, when a low was expected
Bit Error Interrupt Flag — BERRIF is asserted, when the bit error detect circuitry is enabled and if the value
sampled at the RXD input does not match the transmitted value. If the BERRIE interrupt enable bit is set an
interrupt will be generated. The BERRIF bit is cleared by writing a “1” to it.
0 No mismatch detected
1 A mismatch has occurred
Break Detect Interrupt Flag — BKDIF is asserted, if the break detect circuitry is enabled and a break signal is
received. If the BKDIE interrupt enable bit is set an interrupt will be generated. The BKDIF bit is cleared by writing
a “1” to it.
0 No break signal was received
1 A break signal was received
SCI Alternative Status Register 1 (SCIASR1)
SCI Alternative Control Register 1 (SCIACR1)
0
0
7
7
Figure 20-7. SCI Alternative Control Register 1 (SCIACR1)
Figure 20-6. SCI Alternative Status Register 1 (SCIASR1)
= Unimplemented or Reserved
= Unimplemented or Reserved
0
0
0
0
6
6
MC9S12G Family Reference Manual,
Table 20-6. SCIASR1 Field Descriptions
0
0
0
0
5
5
0
0
0
0
4
4
Description
0
0
0
0
3
3
Rev.1.23
BERRV
0
0
0
2
2
BERRIE
BERRIF
Freescale Semiconductor
0
0
1
1
BKDIE
BKDIF
0
0
0
0
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