S9S12GA240F0MLL Freescale Semiconductor, S9S12GA240F0MLL Datasheet - Page 658
S9S12GA240F0MLL
Manufacturer Part Number
S9S12GA240F0MLL
Description
16-bit Microcontrollers - MCU 16BIT 240KB FLASH
Manufacturer
Freescale Semiconductor
Datasheet
1.S9S12G96F0CLL.pdf
(1292 pages)
Specifications of S9S12GA240F0MLL
Rohs
yes
Core
S12
Processor Series
MC9S12G
Data Bus Width
16 bit
Maximum Clock Frequency
25 MHz
Program Memory Size
240 KB
Data Ram Size
4 KB
On-chip Adc
Yes
Operating Supply Voltage
3.13 V to 5.5 V
Operating Temperature Range
- 40 C to + 125 C
Package / Case
LQFP-100
Mounting Style
SMD/SMT
Available stocks
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Manufacturer
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Price
Company:
Part Number:
S9S12GA240F0MLL
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Pulse-Width Modulator (S12PWM8B8CV2)
To calculate the output frequency in left aligned output mode for a particular channel, take the selected
clock source frequency for the channel (A, B, SA, or SB) and divide it by the value in the period register
for that channel.
As an example of a left aligned output, consider the following case:
The output waveform generated is shown in
660
•
•
PWMx Frequency = Clock (A, B, SA, or SB) / PWMPERx
PWMx Duty Cycle (high time as a% of period):
— Polarity = 0 (PPOLx = 0)
— Polarity = 1 (PPOLx = 1)
Clock Source = E, where E = 10 MHz (100 ns period)
PPOLx = 0
PWMPERx = 4
PWMDTYx = 1
PWMx Frequency = 10 MHz/4 = 2.5 MHz
PWMx Period = 400 ns
PWMx Duty Cycle = 3/4 *100% = 75%
Duty Cycle = [(PWMPERx-PWMDTYx)/PWMPERx] * 100%
Duty Cycle = [PWMDTYx / PWMPERx] * 100%
Changing the PWM output mode from left aligned to center aligned output
(or vice versa) while channels are operating can cause irregularities in the
PWM output. It is recommended to program the output mode before
enabling the PWM channel.
PPOLx = 0
PPOLx = 1
E = 100 ns
Figure 19-18. PWM Left Aligned Output Example Waveform
Figure 19-17. PWM Left Aligned Output Waveform
MC9S12G Family Reference Manual,
PWMDTYx
Period = 400 ns
Figure
Period = PWMPERx
Duty Cycle = 75%
NOTE
19-18.
Rev.1.23
Freescale Semiconductor
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