S9S12G240F0CLFR Freescale Semiconductor, S9S12G240F0CLFR Datasheet - Page 424
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S9S12G240F0CLFR
Manufacturer Part Number
S9S12G240F0CLFR
Description
16-bit Microcontrollers - MCU 16BIT 240KB FLASH
Manufacturer
Freescale Semiconductor
Datasheet
1.S9S12G96F0CLL.pdf
(1292 pages)
Specifications of S9S12G240F0CLFR
Rohs
yes
Core
S12
Processor Series
MC9S12G
Data Bus Width
16 bit
Maximum Clock Frequency
25 MHz
Program Memory Size
240 KB
Data Ram Size
4 KB
On-chip Adc
Yes
Operating Supply Voltage
3.13 V to 5.5 V
Operating Temperature Range
- 40 C to + 125 C
Package / Case
LQFP-48
Mounting Style
SMD/SMT
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
S9S12G240F0CLFR
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Analog-to-Digital Converter (ADC10B8CV2)
11.3.2.2
Writes to this register will abort current conversion sequence.
Read: Anytime
Write: Anytime
426
ETRIGCH[3:0]
Module Base + 0x0001
ETRIGSEL
SRES[1:0]
SMP_DIS
Reset
Field
6–5
3–0
W
7
4
R
ETRIGSEL
ATD Control Register 1 (ATDCTL1)
0
7
External Trigger Source Select — This bit selects the external trigger source to be either one of the AD
channels or one of the ETRIG3-0 inputs. See device specification for availability and connectivity of ETRIG3-0
inputs. If a particular ETRIG3-0 input option is not available, writing a 1 to ETRISEL only sets the bit but has
no effect, this means that one of the AD channels (selected by ETRIGCH3-0) is configured as the source for
external trigger. The coding is summarized in
A/D Resolution Select — These bits select the resolution of A/D conversion results. See
coding.
Discharge Before Sampling Bit
0 No discharge before sampling.
1 The internal sample capacitor is discharged before sampling the channel. This adds 2 ATD clock cycles to
External Trigger Channel Select — These bits select one of the AD channels or one of the ETRIG3-0 inputs
as source for the external trigger. The coding is summarized in
1
the sampling time. This can help to detect an open circuit instead of measuring the previous sampled
channel.
If only AN0 should be converted use MULT=0.
SRES1
0
6
SRES1
Figure 11-4. ATD Control Register 1 (ATDCTL1)
0
0
1
1
Table 11-3. ATDCTL1 Field Descriptions
MC9S12G Family Reference Manual,
SRES0
Table 11-4. A/D Resolution Coding
1
5
SRES0
0
1
0
1
SMP_DIS
0
4
Table
Description
11-5.
ETRIGCH3
A/D Resolution
10-bit data
Reserved
Reserved
1
8-bit data
3
Rev.1.23
Table
ETRIGCH2
11-5.
1
2
ETRIGCH1
Freescale Semiconductor
1
1
Table 11-4
ETRIGCH0
for
1
0
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