MAX1363EUB Maxim Integrated, MAX1363EUB Datasheet - Page 11

• Manufacturer Part Number: MAX1363EUB
• Description: Analog to Digital Converters - ADC
• Manufacturer: Maxim Integrated

Specifications of MAX1363EUB

• Number Of Channels: 4/2
• Architecture: SAR
• Conversion Rate: 133 KSPs
• Resolution: 12 bit
• Input Type: Single-Ended/Differential
• Snr: Yes
• Interface Type: I2C, Serial
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Package / Case: uMAX
• Maximum Power Dissipation: 444.4 mW
• Minimum Operating Temperature: - 40 C
• Number Of Converters: 1
• Voltage Reference: 4.096 V

where R
R
t
2 / f
The MAX1363/MAX1364 feature input-tracking circuitry
with a 5MHz small-signal bandwidth. The 5MHz input
bandwidth makes it possible to digitize high-speed
transient events and measure periodic signals with
bandwidths exceeding the ADC’s sampling rate by
using undersampling techniques. To avoid high-fre-
quency signals from aliasing into the frequency band of
interest, use anti-aliasing filtering.
Internal protection diodes clamp the analog inputs to V
and GND. These diodes allow the analog inputs to swing
from (GND - 0.3V) to (V
age to the device. For accurate conversions, the inputs
must remain within 50mV below GND or above V
The SE/DIF of the configuration byte configures the
MAX1363/MAX1364 analog-input circuitry for single-
ended or differential input. In single-ended mode (SE/DIF
= 1), the digital conversion results are the difference
between the analog input selected by CS[3:0] and GND.
In differential mode (SE/DIF = 0), the digital conversion
results are the difference between the plus and the minus
analog inputs selected by CS[3:0] (see Tables 5 and 6).
Unipolar mode sets the differential input range from 0 to
V
mode causes the digital output code to be zero.
Selecting bipolar mode sets the differential input range
to ±V
lar mode and two’s complement in bipolar mode. (See
the Transfer Functions section.)
In single-ended mode the MAX1363/MAX1364 always
operate in unipolar mode. The analog inputs are inter-
nally referenced to GND with a full-scale input range
from 0 to V
SEL[2:0] of the setup byte controls the reference and
the AIN3/REF configuration. When AIN3/REF is config-
ured as a reference input or reference output (SEL1 =
1), differential conversions on AIN3/REF appear as if
AIN3/REF is connected to GND. A single-ended conver-
sion in scan mode on AIN3/REF is ignored by an internal
limiter that sets the highest available channel at AIN2.
ACQ
REF
4-Channel, 12-Bit System Monitors with Programmable
IN
SCL
= 2.5kΩ, and C
. A negative differential analog input in unipolar
REF
= 1.5 / f
.
SOURCE
/ 2. The digital output code is binary in unipo-
Analog-Input Range and Protection
REF
SCL
(Table 7).
Single-Ended/Differential Input
is the analog-input source impedance,
, and for external clock mode t
______________________________________________________________________________________
IN
= 22pF. For internal clock mode,
DD
Analog-Input Bandwidth
+ 0.3V) without causing dam-
Trip Window and SMBus Alert Response
Unipolar/Bipolar
Reference
DD
ACQ
.
DD
=
The internal reference is 2.048V for the MAX1363 and
4.096V for the MAX1364. SEL1 of the setup byte con-
trols whether AIN3/REF is used for an analog input or a
reference. Decouple AIN3/REF to GND with a 0.1µF
capacitor and a 2kΩ resistor in series with the capaci-
tor. When AIN3/REF is configured as an internal refer-
ence output (SEL[1:0] = 11). See the Typical Operating
Circuit . Once powered up, the reference remains on
until reconfigured. Do not use the reference to supply
current for external circuitry.
The external reference ranges from 1V to V
imum conversion accuracy, the reference must deliver
40µA and have an impedance of 500Ω or less. For
noisy or high-output-impedance references, insert a
0.1µF bypass capacitor to GND as close to AIN3/REF
as possible.
The clock mode determines the conversion clock and
the data acquisition and conversion time. The clock
mode also affects the scan mode. The state of the
setup byte’s INT/EXT clock bit determines the clock
mode. At power-up, the MAX1363/MAX1364 default to
internal clock mode (INT/EXT clock = 0).
See the Configuration/Setup Bytes (Write Cycle) section.
In internal clock mode (CLK = 0), the MAX1363/
MAX1364 use an internal oscillator for the conversion
clock. The MAX1363/MAX1364 begin tracking the analog
input after a valid address on the eighth rising edge of the
clock. On the falling edge of the ninth clock, the analog
signal is acquired and the conversion begins. While con-
verting, the MAX1363/MAX1364 hold SCL low (clock
stretching). After completing the conversion, the results
are stored in internal memory. For scan-mode configura-
tions with multiple conversions (see the Scan Modes sec-
tion), all conversions happen in succession with each
additional result stored in memory. Once all conversions
are complete, the MAX1363/MAX1364 release SCL,
allowing it to go high. The master can now clock the
results out in the same order as the scan conversion.
The converted results are read back in a FIFO
sequence. If AIN3/REF is configured as a reference
input or output, AIN3/REF is excluded from multichan-
nel scan. If reading continues past the final result
stored in memory, the pointer wraps around and points
to the first result. Only the current conversion results are
read from memory. The MAX1363/MAX1364 must be
addressed with a read command to obtain new conver-
sion results.
External Reference
Internal Reference
Clock Modes
Internal Clock
DD
. For max-
11