MAX1363EUB Maxim Integrated, MAX1363EUB Datasheet - Page 9

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MAX1363EUB

Manufacturer Part Number
MAX1363EUB
Description
Analog to Digital Converters - ADC
Manufacturer
Maxim Integrated
Datasheet

Specifications of MAX1363EUB

Number Of Channels
4/2
Architecture
SAR
Conversion Rate
133 KSPs
Resolution
12 bit
Input Type
Single-Ended/Differential
Snr
Yes
Interface Type
I2C, Serial
Operating Supply Voltage
2.7 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Package / Case
uMAX
Maximum Power Dissipation
444.4 mW
Minimum Operating Temperature
- 40 C
Number Of Converters
1
Voltage Reference
4.096 V

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MAX1363EUB+
Manufacturer:
MAXIM/美信
Quantity:
20 000
The MAX1363/MAX1364 4-channel ADCs use succes-
sive-approximation conversion techniques and fully dif-
ferential input track/hold (T/H) circuitry to capture and
convert analog signals to a serial 12-bit digital output.
The MAX1363/MAX1364 feature a monitor mode with
programmable trip thresholds and window comparator.
The monitor function asserts an interrupt when any
channel violates the programmed upper or lower
thresholds. SMBus alert response allows the host
microcontroller (µC) to quickly identify which device
caused the interrupt. A programmable delay between
monitoring intervals lowers power consumption at lower
monitor rates.
The MAX1363/MAX1364 integrate an internal voltage
reference and clock. The software configures the ana-
log inputs for unipolar/bipolar and single-ended/fully
differential operation. Integrated first-in/first-out (FIFO)
allows conversion of all channels, or eight conversions
Figure 1a. F/S-Mode 2-Wire Serial-Interface Timing
Figure 1b. HS-Mode 2-Wire Serial-Interface Timing
4-Channel, 12-Bit System Monitors with Programmable
SDA
SCL
SDA
SCL
S
t
SU.STA
Sr
t
HD.STA
t
LOW
_______________________________________________________________________________________
t
LOW
t
Detailed Description
R
t
RCL
t
SU.DAT
t
SU.DAT
t
HIGH
t
HIGH
1
Trip Window and SMBus Alert Response
t
F
t
FCL
t
HD.DAT
t
HD.DAT
HS-MODE
t
SU.STA
t
SU.STA
on a selected channel to reduce interface overhead. An
I
fast, and high-speed (1.7MHz) modes.
Figure 2. Load Circuits
2
C-compatible serial interface complies with standard,
Sr
Sr
t
HD.STA
t
HD.STA
SDA
ACK
ACK
9
9
t
t
RCL1
SU.STO
V
t
DD
SU.STO
I
I
t
RDA
OL
OH
t
R
P
400pF
V
P
OUT
t
BUF
F/S-MODE
t
F
S
S
t
FDA
9

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