S9S12P64J0CFTR Freescale Semiconductor, S9S12P64J0CFTR Datasheet - Page 217

• Manufacturer Part Number: S9S12P64J0CFTR
• Description: 16-bit Microcontrollers - MCU 16-bit 64K Flash
• Manufacturer: Freescale Semiconductor

Specifications of S9S12P64J0CFTR

• Rohs: yes
• Core: S12
• Processor Series: MC9S12P
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 25 MHz
• Program Memory Size: 64 KB
• Data Ram Size: 4 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 3.15 V to 5.5 V
• Operating Temperature Range: - 40 C to + 125 C
• Package / Case: QFN-48
• Mounting Style: SMD/SMT

7.3.2.9
This register controls the COP (Computer Operating Properly) watchdog.
The clock source for the COP is either IRCCLK or OSCCLK depending on the setting of the
COPOSCSEL bit. In Stop Mode with PSTP=1 (Pseudo Stop Mode), COPOSCSEL=1 and PCE=1 the COP
continues to run, else the COP counter halts in Stop Mode.
Read: Anytime
Write:
When a non-zero value is loaded from Flash to CR[2:0] the COP time-out period is started.
A change of the COPOSCSEL bit (writing a different value or loosing UPOSC status) re-starts the COP
time-out period.
In normal mode the COP time-out period is restarted if either of these conditions is true:
In special mode, any write access to CPMUCOP register restarts the COP time-out period.
Freescale Semiconductor
0x003C
After de-assert of System Reset the values are automatically loaded from the Flash memory. See Device specification for
Reset
1. RSBCK: anytime in special mode; write to “1” but not to “0” in normal mode
2. WCOP, CR2, CR1, CR0:
1. Writing a non-zero value to CR[2:0] (anytime in special mode, once in normal mode) with
2. Writing WCOP bit (anytime in special mode, once in normal mode) with WRTMASK = 0.
3. Changing RSBCK bit from “0” to “1”.
details.
W
R
— Anytime in special mode, when WRTMASK is 0, otherwise it has no effect
— Write once in normal mode, when WRTMASK is 0, otherwise it has no effect.
WRTMASK = 0.
– Writing CR[2:0] to “000” has no effect, but counts for the “write once” condition.
– Writing WCOP to “0” has no effect, but counts for the “write once” condition.
WCOP
S12CPMU COP Control Register (CPMUCOP)
F
7
= Unimplemented or Reserved
RSBCK
Figure 7-12. S12CPMU COP Control Register (CPMUCOP)
0
6
WRTMASK
S12P-Family Reference Manual, Rev. 1.13
0
0
5
0
0
4
S12 Clock, Reset and Power Management Unit (S12CPMU)
0
0
3
CR2
F
2
CR1
F
1
CR0
F
0
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