S9S12P64J0CFTR Freescale Semiconductor, S9S12P64J0CFTR Datasheet - Page 49

• Manufacturer Part Number: S9S12P64J0CFTR
• Description: 16-bit Microcontrollers - MCU 16-bit 64K Flash
• Manufacturer: Freescale Semiconductor

Specifications of S9S12P64J0CFTR

• Rohs: yes
• Core: S12
• Processor Series: MC9S12P
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 25 MHz
• Program Memory Size: 64 KB
• Data Ram Size: 4 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 3.15 V to 5.5 V
• Operating Temperature Range: - 40 C to + 125 C
• Package / Case: QFN-48
• Mounting Style: SMD/SMT

Chapter 2 Port Integration Module (S12PPIMV1)
Revision History
2.1
2.1.1
The S12P Family Port Integration Module establishes the interface between the peripheral modules and
the I/O pins for all ports. It controls the electrical pin properties as well as the signal prioritization and
multiplexing on shared pins.
This section covers:
Most I/O pins can be configured by register bits to select data direction and drive strength, to enable and
select pull-up or pull-down devices.
Freescale Semiconductor
(Item No.)
Rev. No.
V01.00
V01.01
V01.02
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Port A and B used as general purpose I/O
Port E associated with the IRQ, XIRQ interrupt inputs
Port T associated with 1 timer module
Port S associated with 1 SCI module
Port M associated with 1 MSCAN and 1 SPI module
Port P connected to the PWM - inputs can be used as an external interrupt source
Port J used as general purpose I/O - inputs can be used as an external interrupt source
Port AD associated with one 10-channel ATD module
Introduction
(Submitted By)
Overview
05 May 2008
19 Mar 2008
12 Jan 2009
This section assumes the availability of all features (80-pin package option).
Some functions are not available on lower pin count package options. Refer
to the pin-out summary section.
Date
Sections
Affected
S12P-Family Reference Manual, Rev. 1.13
Initial version
Corrected mistakes in Port J register and field names
Corrected PERxAD register descriptions
Replaced VREG_API with API_EXTCLK
Minor corrections
NOTE
Substantial Change(s)
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