S912XEP100J5VAGR Freescale Semiconductor, S912XEP100J5VAGR Datasheet - Page 305

• Manufacturer Part Number: S912XEP100J5VAGR
• Description: 16-bit Microcontrollers - MCU 16-bit 1000K Flash
• Manufacturer: Freescale Semiconductor

Specifications of S912XEP100J5VAGR

• Rohs: yes
• Core: HCS12X
• Processor Series: MC9S12
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 1000 KB
• Data Ram Size: 64 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 3.3 V to 5 V
• Operating Temperature Range: - 40 C to + 125 C
• Package / Case: LQFP-144
• Mounting Style: SMD/SMT

Chapter 8
S12X Debug (S12XDBGV3) Module
8.1
The S12XDBG module provides an on-chip trace buffer with flexible triggering capability to allow non-
intrusive debug of application software. The S12XDBG module is optimized for the S12X 16-bit
architecture and allows debugging of CPU12Xand XGATE module operations.
Typically the S12XDBG module is used in conjunction with the S12XBDM module, whereby the user
configures the S12XDBG module for a debugging session over the BDM interface. Once configured the
S12XDBG module is armed and the device leaves BDM Mode returning control to the user program,
which is then monitored by the S12XDBG module. Alternatively the S12XDBG module can be configured
over a serial interface using SWI routines.
8.1.1
Freescale Semiconductor
Revision
Number
V03.20
V03.21
V03.22
V03.23
V03.24
V03.25
V03.26
WORD
Term
BDM
DUG
COF
Introduction
Revision Date
Glossary
14 Sep 2007
12 Nov 2007
13 Nov 2007
14 May 2008
12 Sep 2012
23 Oct 2007
04 Jan 2008
Change Of Flow.
Change in the program flow due to a conditional branch, indexed jump or interrupt
Background Debug Mode
Device User Guide, describing the features of the device into which the DBG is integrated
16-bit data entity
8.3.2.7/8-317
8.4.2.2/8-329
8.4.2.4/8-330
8.4.5.2/8-334
8.4.5.5/8-341
8.4.5.3/8-336
Sections
Affected
General
General
General
MC9S12XE-Family Reference Manual Rev. 1.25
Table 8-2. Glossary Of Terms
Table 8-1. Revision History
- Clarified reserved State Sequencer encodings.
- Added single databyte comparison limitation information
- Added statement about interrupt vector fetches whilst tagging.
- Removed LOOP1 tracing restriction NOTE.
- Added pin reset effect NOTE.
- Text readability improved, typo removed.
- Corrected bit name.
- Updated Revision History Table format. Corrected other paragraph formats.
- Added missing full stops. Removed redundant quotation marks.
Definition
Description of Changes
305