S912XEP100J5VAGR Freescale Semiconductor, S912XEP100J5VAGR Datasheet - Page 369
S912XEP100J5VAGR
Manufacturer Part Number
S912XEP100J5VAGR
Description
16-bit Microcontrollers - MCU 16-bit 1000K Flash
Manufacturer
Freescale Semiconductor
Datasheet
1.S912XEG128J2MAL.pdf
(1324 pages)
Specifications of S912XEP100J5VAGR
Rohs
yes
Core
HCS12X
Processor Series
MC9S12
Data Bus Width
16 bit
Maximum Clock Frequency
50 MHz
Program Memory Size
1000 KB
Data Ram Size
64 KB
On-chip Adc
Yes
Operating Supply Voltage
3.3 V to 5 V
Operating Temperature Range
- 40 C to + 125 C
Package / Case
LQFP-144
Mounting Style
SMD/SMT
Available stocks
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Price
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10.3.1.11 XGATE Condition Code Register (XGCCR)
The XGCCR register
Module Base +0x001D
Read: In debug mode if unsecured and not idle (XGCHID ≠ 0x00)
Write: In debug mode if unsecured and not idle (XGCHID ≠ 0x00)
Freescale Semiconductor
XGSEMM[7:0]
XGSEM[7:0]
Reset
Field
15–8
Field
XGN
XGV
XGC
XGZ
7–0
3
2
1
0
W
R
0
0
Semaphore Mask — These bits control the write access to the XGSEM bits.
Read:
These bits will always read "0".
Write:
0 Disable write access to the XGSEM in the same bus cycle
1 Enable write access to the XGSEM in the same bus cycle
Semaphore Bits — These bits indicate whether a semaphore is locked by the S12X_CPU. A semaphore can
be attempted to be set by writing a "1" to the XGSEM bit and to the corresponding XGSEMM bit in the same
write access. Only unlocked semaphores can be set. A semaphore can be cleared by writing a "0" to the
XGSEM bit and a "1" to the corresponding XGSEMM bit in the same write access.
Read:
0 Semaphore is unlocked or locked by the RISC core
1 Semaphore is locked by the S12X_CPU
Write:
0 Clear semaphore if it was locked by the S12X_CPU
1 Attempt to lock semaphore by the S12X_CPU
7
Sign Flag — The RISC core’s Sign flag
Zero Flag — The RISC core’s Zero flag
Overflow Flag — The RISC core’s Overflow flag
Carry Flag — The RISC core’s Carry flag
= Unimplemented or Reserved
(Figure
Figure 10-13. XGATE Condition Code Register (XGCCR)
0
0
6
10-13) provides access to the RISC core’s condition code register.
MC9S12XE-Family Reference Manual Rev. 1.25
Table 10-12. XGSEM Field Descriptions
Table 10-13. XGCCR Field Descriptions
0
0
5
0
0
4
Description
Description
XGN
0
3
XGZ
0
2
Chapter 10 XGATE (S12XGATEV3)
XGV
0
1
XGC
0
0
369
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