SiM3C167-B-GM Silicon Labs, SiM3C167-B-GM Datasheet - Page 43

• Manufacturer Part Number: SiM3C167-B-GM
• Description: ARM Microcontrollers - MCU 256KB LGA92
• Manufacturer: Silicon Labs

Specifications of SiM3C167-B-GM

• Rohs: yes
• Core: ARM Cortex M3
• Processor Series: SIM3C1xx
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 80 MHz
• Program Memory Size: 256 KB
• Data Ram Size: 47 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.6 V
• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: LGA-92
• Mounting Style: SMD/SMT
• Interface Type: 2 x I2C, I2S, 3 x SPI, 2 x USART, 2 x UART
• Number Of Programmable I/os: 80
• Number Of Timers: 17 x 32 bit
• Supply Voltage - Max: 3.6 V

4.6.4. SPI (SPI0, SPI1)
SPI is a 3- or 4-wire communication interface that includes a clock, input data, output data, and an optional select
signal.
The SPI module includes the following features:
4.6.5. I2C (I2C0, I2C1)
The I2C interface is a two-wire, bi-directional serial bus. The two clock and data signals operate in open-drain
mode with external pull-ups to support automatic bus arbitration.
Reads and writes to the interface are byte oriented with the I2C interface autonomously controlling the serial
transfer of the data. Data can be transferred at up to 1/8th of the APB clock as a master or slave, which can be
faster than allowed by the I2C specification, depending on the clock source used. A method of extending the clock-
low duration is available to accommodate devices with different speed capabilities on the same bus.
The I2C interface may operate as a master and/or slave, and may function on a bus with multiple masters. The I2C
provides control of SDA (serial data), SCL (serial clock) generation and synchronization, arbitration logic, and start/
stop control and generation.
The I2C module includes the following features:
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Internal transmit and receive FIFOs with flush capability and support for byte, half-word, and word reads
and writes.
Data bit lengths from 5 to 9 bits.
Programmable inter-packet transmit delays.
Auto-baud detection with support for the LIN SYNC byte.
Automatic parity generation (with enable).
Automatic start and stop generation.
Transmit and receive hardware flow-control.
Independent inversion correction for TX, RX, RTS, and CTS signals.
IrDA modulation and demodulation with programmable pulse widths.
Smartcard ACK/NACK support.
Parity error, frame error, overrun, and underrun detection.
Multi-master and half-duplex support.
Multiple loop-back modes supported.
Supports 3- or 4-wire master or slave modes.
Supports up to 10 MHz clock in master mode and 5 MHz clock in slave mode.
Support for all clock phase and slave select (NSS) polarity modes.
16-bit programmable clock rate.
Programmable MSB-first or LSB-first shifting.
8-byte FIFO buffers for both transmit and receive data paths to support high speed transfers.
Programmable FIFO threshold level to request data service for DMA transfers.
Support for multiple masters on the same data lines.
Standard (up to 100 kbps) and Fast (400 kbps) transfer speeds.
Can operate down to APB clock divided by 32768 or up to APB clock divided by 8.
Support for master, slave, and multi-master modes.
Hardware synchronization and arbitration for multi-master mode.
Clock low extending (clock stretching) to interface with faster masters.
Hardware support for 7-bit slave and general call address recognition.
Firmware support for 10-bit slave address decoding.
Ability to disable all slave states.
Programmable clock high and low period.
Programmable data setup/hold times.
Rev.1.0
SiM3C1xx
43