SiM3C167-B-GM Silicon Labs, SiM3C167-B-GM Datasheet - Page 48

• Manufacturer Part Number: SiM3C167-B-GM
• Description: ARM Microcontrollers - MCU 256KB LGA92
• Manufacturer: Silicon Labs

Specifications of SiM3C167-B-GM

• Rohs: yes
• Core: ARM Cortex M3
• Processor Series: SIM3C1xx
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 80 MHz
• Program Memory Size: 256 KB
• Data Ram Size: 47 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.6 V
• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: LGA-92
• Mounting Style: SMD/SMT
• Interface Type: 2 x I2C, I2S, 3 x SPI, 2 x USART, 2 x UART
• Number Of Programmable I/os: 80
• Number Of Timers: 17 x 32 bit
• Supply Voltage - Max: 3.6 V

SiM3C1xx
4.9. Security
The peripherals on the SiM3C1xx devices have a register lock and key mechanism that prevents any undesired
accesses of the peripherals from firmware. Each bit in the PERIPHLOCKx registers controls a set of peripherals. A
key sequence must be written in order to the KEY register to modify any of the bits in PERIPHLOCKx. Any
subsequent write to KEY will then inhibit any accesses of PERIPHLOCKx until it is unlocked again through KEY.
Reading the KEY register indicates the current status of the PERIPHLOCKx lock state.
If a peripheral’s registers are locked, all writes will be ignored. The registers can always be read, regardless of the
peripheral’s lock state.
4.10. On-Chip Debugging
The SiM3C1xx devices include JTAG and Serial Wire programming and debugging interfaces and ETM for
instruction trace. The JTAG interface is supported on SiM3C1x7 and SiM3C1x6 devices only, and does not include
boundary scan capabiites. The ETM interface is supported on SiM3C1x7 devices. The JTAG and ETM interfaces
can be optionally enabled to provide more visibility while debugging at the cost of using several Port I/O pins.
Additionally, if the core is configured for Serial Wire (SW) mode and not JTAG, then the Serial Wire Viewer (SWV)
is available to provide a single pin to send out TPIU messages on SiM3C1x7 and SiM3C1x6 devices.
Most peripherals have the option to halt or continue functioning when the core halts in debug mode.
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KEY
Peripheral Lock and Key
PERIPHLOCK0
PERIPHLOCK1
Rev.1.0
EPCA0, PCA0/1
SARADC0/1
USART0/1,
TIMER0/1
UART0/1
SPI0/1/2
I2C0/1
SSG0