MK30DX64VLK7R Freescale Semiconductor, MK30DX64VLK7R Datasheet
MK30DX64VLK7R
Specifications of MK30DX64VLK7R
Related parts for MK30DX64VLK7R
MK30DX64VLK7R Summary of contents
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... Low-power hardware touch sensor interface (TSI) – General-purpose input/output Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. © 2012 Freescale Semiconductor, Inc. Document Number: K30P100M72SF1 Rev. 3, 11/2012 K30P100M72SF1 • Analog modules – ...
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... DSPI switching specifications (full voltage range).52 6.8.4 I2C switching specifications..................................54 6.8.5 UART switching specifications..............................54 6.8.6 I2S/SAI Switching Specifications..........................54 6.9 Human-machine interfaces (HMI)......................................58 6.9.1 TSI electrical specifications...................................58 6.9.2 LCD electrical characteristics................................59 7 Dimensions...............................................................................60 7.1 Obtaining package dimensions.........................................60 8 Pinout........................................................................................61 8.1 K30 Signal Multiplexing and Pin Assignments..................61 8.2 K30 Pinouts.......................................................................66 9 Revision History........................................................................68 Freescale Semiconductor, Inc. ...
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... Qualification status K## Kinetis family A Key attribute M Flash memory type K30 Sub-Family Data Sheet, Rev. 3, 11/2012. Freescale Semiconductor, Inc. www.freescale.com and perform a part number search for Description • Fully qualified, general market flow • Prequalification • K30 • Cortex-M4 w/ DSP • Cortex-M4 w/ DSP and FPU • ...
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... LQ = 144 LQFP ( mm) • 144 MAPBGA ( mm) • 256 MAPBGA ( mm) • MHz • MHz • 100 MHz • 120 MHz • 150 MHz • Tape and reel • (Blank) = Trays Values Freescale Semiconductor, Inc. ...
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... An attribute is a specified value or range of values for a technical characteristic that are guaranteed, regardless of whether you meet the operating requirements. 3.3.1 Example This is an example of an attribute: Symbol Description CIN_D Input capacitance: digital pins K30 Sub-Family Data Sheet, Rev. 3, 11/2012. Freescale Semiconductor, Inc. Min. Max. 0.9 1.1 Min. Max. 10 130 Min. ...
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... V core supply DD voltage 3.5 Result of exceeding a rating Measured characteristic K30 Sub-Family Data Sheet, Rev. 3, 11/2012. 6 Min. –0.3 1.2 The likelihood of permanent chip failure increases rapidly as soon as a characteristic begins to exceed one of its operating ratings. Operating rating Max. Unit V Freescale Semiconductor, Inc. ...
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... Typical values are provided as design guidelines and are neither tested nor guaranteed. K30 Sub-Family Data Sheet, Rev. 3, 11/2012. Freescale Semiconductor, Inc. Normal operating range Degraded operating range - No permanent failure - No permanent failure ...
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... Typical values assume you meet the following conditions (or other conditions as specified): Symbol T Ambient temperature A V 3.3 V supply voltage DD K30 Sub-Family Data Sheet, Rev. 3, 11/2012. 8 Min. Typ 1.00 1.05 1.10 V (V) DD Description Value 25 3.3 Max. Unit 130 µ 150 °C 105 °C 25 °C –40 °C Unit °C V Freescale Semiconductor, Inc. ...
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... Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components. 4.4 Voltage and current operating ratings Symbol Description V Digital supply voltage DD K30 Sub-Family Data Sheet, Rev. 3, 11/2012. Freescale Semiconductor, Inc. Min. –55 — Min. — Min. -2000 -500 -100 Table continues on the next page ...
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... Nonswitching electrical specifications K30 Sub-Family Data Sheet, Rev. 3, 11/2012. 10 Min. Max. Unit — 185 mA –0.3 5.5 V –0 0 – – –0.3 3.8 V Freescale Semiconductor, Inc. ...
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... If these limits cannot be observed then a current limiting resistor is required. The negative DC injection current limiting resistor is calculated as R=(V calculated as R=(V -V )/|I |. Select the larger of these two calculated resistances. IN AIO_MAX IC K30 Sub-Family Data Sheet, Rev. 3, 11/2012. Freescale Semiconductor, Inc. Min. 1.71 1.71 –0.1 –0.1 1.71 0.7 × V 0.75 × V — ...
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... K30 Sub-Family Data Sheet, Rev. 3, 11/2012. 12 supply LVD and POR operating requirements Min. 0.8 2.48 2.62 2.72 2.82 2.92 — 1.54 1.74 1.84 1.94 2.04 — 0.97 900 Min. 0.8 Typ. Max. Unit Notes 1.1 1.5 V 2.56 2.64 V 2.70 2.78 V 2.80 2.88 V 2.90 2.98 V 3.00 3.08 V ±80 — mV 1.60 1.66 V 1.80 1.86 V 1.90 1.96 V 2.00 2.06 V 2.10 2.16 V ±60 — mV 1.00 1.03 V 1000 1100 μs Typ. Max. Unit Notes 1.1 1.5 V Freescale Semiconductor, Inc ...
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... Power mode transition operating behaviors All specifications except t POR assume this clock configuration: • CPU and system clocks = 72 MHz • Bus clock = 36 MHz • Flash clock = 24 MHz K30 Sub-Family Data Sheet, Rev. 3, 11/2012. Freescale Semiconductor, Inc. Min. = -9mA V – 0 -3mA V – ...
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... Table continues on the next page... Max. Unit Notes 300 μs 1 112 μs 74 μs 73 μs 5.9 μs 5.8 μs 4.2 μs Max. Unit Notes See note — — — — Freescale Semiconductor, Inc. ...
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... I Average current with RTC and 32kHz disabled at DD_VBAT 3.0 V • @ –40 to 25°C • @ 70°C • @ 105°C K30 Sub-Family Data Sheet, Rev. 3, 11/2012. Freescale Semiconductor, Inc. Min. Typ. — 0.61 — 0.35 — 0.384 — 0.628 — ...
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... Code execution from flash with cache enabled • For the ALLOFF curve, all peripheral clocks are disabled except FTFL K30 Sub-Family Data Sheet, Rev. 3, 11/2012. 16 Min. Typ. Max. Unit — 0.57 0.67 μA — 0.90 1.2 μA — 2.4 3.5 μA — 0.67 0.94 μA — 1.0 1.4 μA — 2.7 3.9 μA Freescale Semiconductor, Inc. Notes 10 ...
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... Figure 2. Run mode supply current vs. core frequency K30 Sub-Family Data Sheet, Rev. 3, 11/2012. Freescale Semiconductor, Inc. General 17 ...
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... Go to www.freescale.com. 2. Perform a keyword search for “EMC design.” 5.2.7 Capacitance attributes Symbol Description C Input capacitance: analog pins IN_A C Input capacitance: digital pins IN_D K30 Sub-Family Data Sheet, Rev. 3, 11/2012. 18 Table 7. Capacitance attributes Min. Max. Unit — — Freescale Semiconductor, Inc. ...
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... Asynchronous path GPIO pin interrupt pulse width (digital glitch filter disabled, analog filter disabled) — Asynchronous path External reset pulse width (digital glitch filter disabled) K30 Sub-Family Data Sheet, Rev. 3, 11/2012. Freescale Semiconductor, Inc. Min. Normal run mode — — ...
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... K30 Sub-Family Data Sheet, Rev. 3, 11/2012. 20 Min. Max. Unit 2 — Bus clock cycles — — — — — — — — Min. Max. –40 125 –40 105 Freescale Semiconductor, Inc. Notes 4 5 Unit °C °C ...
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... The value includes the thermal resistance of the interface material between the top of the package and the cold plate. 6. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions—Natural Convection (Still Air). K30 Sub-Family Data Sheet, Rev. 3, 11/2012. Freescale Semiconductor, Inc. 121 100 LQFP Unit MAPBGA 74 52 ° ...
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... Data setup s T Data hold h Figure 4. TRACE_CLKOUT specifications TRACE_CLKOUT TRACE_D[3:0] Figure 5. Trace data specifications K30 Sub-Family Data Sheet, Rev. 3, 11/2012. 22 Min. Frequency dependent 2 2 — — Max. Unit MHz — ns — — ns — Freescale Semiconductor, Inc. ...
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... TCLK clock pulse width • Boundary Scan • JTAG and CJTAG • Serial Wire Debug J4 TCLK rise and fall times K30 Sub-Family Data Sheet, Rev. 3, 11/2012. Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Table continues on the next page... Min. Max. Unit 2.7 3 ...
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... K30 Sub-Family Data Sheet, Rev. 3, 11/2012 Figure 6. Test clock input timing Min. Max. Unit 20 — — ns — — — ns 1.4 — ns — 22.1 ns — 22.1 ns 100 — — Input data valid Output data valid Output data valid Freescale Semiconductor, Inc. ...
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... TCLK J13 TRST 6.2 System modules There are no specifications necessary for the device's system modules. 6.3 Clock modules K30 Sub-Family Data Sheet, Rev. 3, 11/2012. Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors J11 J12 J11 Figure 8. Test Access Port timing J14 Figure 9. TRST timing ...
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... MHz — 5 MHz — — kHz — — kHz — 39.0625 kHz 25 MHz 2, 50 MHz 75 MHz 100 MHz — MHz 4, — MHz — MHz — MHz Freescale Semiconductor, Inc ...
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... BLPI) to PLL enabled (PBE, PEE crystal/resonator is being used as the reference, this specification assumes it is already running. 6.3.2 Oscillator electrical specifications This section provides the electrical characteristics of the module. K30 Sub-Family Data Sheet, Rev. 3, 11/2012. Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Min. Typ. — ...
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... MΩ — MΩ — MΩ — MΩ — kΩ — kΩ — kΩ — kΩ Freescale Semiconductor, Inc. ...
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... When transitioning from FBE to FEI mode, restrict the frequency of the input clock so that, when it is divided by FRDIV, it remains within the limits of the DCO input clock frequency. 3. Proper PC board layout procedures must be followed to achieve specifications. K30 Sub-Family Data Sheet, Rev. 3, 11/2012. Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Min. — ...
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... The voltage of the applied BAT Min. Typ. Max. 1.71 — 3.6 — 100 — — — 0.6 — Typ. Max. Unit Notes 32.768 — kHz 1000 — ms — BAT Freescale Semiconductor, Inc. Unit V MΩ ...
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... Read 1s All Blocks execution time rd1all t Read Once execution time rdonce t Program Once execution time pgmonce t Erase All Blocks execution time ersall K30 Sub-Family Data Sheet, Rev. 3, 11/2012. Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Min. Typ. — 7.5 — 13 — 52 — 104 Min ...
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... Freescale Semiconductor, Inc ...
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... Write endurance to FlexRAM for EEPROM When the FlexNVM partition code is not set to full data flash, the EEPROM data set size can be set to any of several non-zero values. K30 Sub-Family Data Sheet, Rev. 3, 11/2012. Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Min. Typ. ...
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... Write_efficiency — • 0.25 for 8-bit writes to FlexRAM • 0.50 for 16-bit or 32-bit writes to FlexRAM • n — data flash cycling endurance (the following graph assumes 10,000 nvmcycd cycles) K30 Sub-Family Data Sheet, Rev. 3, 11/2012. 34 EEESPLIT × EEESIZE × Write_efficiency × n nvmcycd Freescale Semiconductor, Inc. ...
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... EZP_CK high to EZP_D input invalid (hold) EP7 EZP_CK low to EZP_Q output valid EP8 EZP_CK low to EZP_Q output invalid (hold) EP9 EZP_CS negation to EZP_Q tri-state K30 Sub-Family Data Sheet, Rev. 3, 11/2012. Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Min. Max. 1.71 3.6 — f ...
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... All other ADC channels meet the 13-bit differential/12-bit single-ended accuracy specifications. K30 Sub-Family Data Sheet, Rev. 3, 11/2012. 36 EP3 EP2 EP4 EP9 EP8 EP7 EP5 EP6 Figure 11. EzPort Timing Diagram Table 24 and Table 25 are achievable on the Table 26 Freescale Semiconductor, Inc. and ...
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... To use the maximum ADC conversion clock frequency, the ADHSC bit must be set and the ADLPC bit must be clear. 5. For guidelines and examples of conversion rate calculation, download the K30 Sub-Family Data Sheet, Rev. 3, 11/2012. Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Min. ...
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... SIMPLIFIED CHANNEL SELECT CIRCUIT ADC SAR ENGINE R ADIN R ADIN R ADIN R ADIN C ADIN , REFL SSA 2 Max. Unit Notes 1 3 MHz ADACK f ADACK 6.1 MHz 7.3 MHz 9.5 MHz 4 ±6.8 LSB 5 ±2.1 4 -1.1 to +1.9 LSB 5 -0.3 to 0.5 4 -2.7 to +1.9 LSB 5 -0.7 to +0.5 4 -5.4 LSB V = ADIN V DDA -1.8 5 Freescale Semiconductor, Inc. ...
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... ADC conversion clock < 16 MHz, Max hardware averaging (AVGE = %1, AVGS = %11) 6. Input data is 100 Hz sine wave. ADC conversion clock < 12 MHz. 7. Input data is 1 kHz sine wave. ADC conversion clock < 12 MHz. K30 Sub-Family Data Sheet, Rev. 3, 11/2012. Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors = ...
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... Peripheral operating requirements and behaviors Figure 13. Typical ENOB vs. ADC_CLK for 16-bit differential mode Figure 14. Typical ENOB vs. ADC_CLK for 16-bit single-ended mode K30 Sub-Family Data Sheet, Rev. 3, 11/2012. 40 Freescale Semiconductor, Inc. ...
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... Recommended ADC setting is: ADLSMP=1, ADLSTS MHz ADC clock. 7. ADC clock = 18 MHz, ADLSMP = 1, ADLST = 00, ADHSC = 1 8. ADC clock = 12 MHz, ADLSMP = 1, ADLST = 01, ADHSC = 1 K30 Sub-Family Data Sheet, Rev. 3, 11/2012. Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors 1 Min. Typ. Max. ...
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... VDDA 60Hz — 500mVpp, — 50Hz, VCM 100Hz — mV Output offset = V *(Gain+1) OFS 10 µ ppm/°C 42 ppm/°C 0.21 %/V V from 1.71 DDA to 3.6V 0.31 %/ leakage AS In current (refer to the MCU's voltage and current operating ratings) Freescale Semiconductor, Inc. ...
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... PGA reference voltage and gain setting. 6.6.2 CMP and 6-bit DAC electrical specifications Table 28. Comparator and 6-bit DAC electrical specifications Symbol Description V Supply voltage DD K30 Sub-Family Data Sheet, Rev. 3, 11/2012. Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Min. Typ. where REFPGA 80 ...
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... DD Typ. Max. Unit — 200 μA — 20 μA — — — — — — mV — — V — 0 200 ns 250 600 ns — 40 μs 7 — μA 3 — 0.5 LSB — 0.3 LSB Freescale Semiconductor, Inc. ...
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... Figure 15. Typical hysteresis vs. Vin level (VDD=3.3V, PMODE=0) K30 Sub-Family Data Sheet, Rev. 3, 11/2012. Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors 1 1.3 1.6 1.9 2.2 Vin level (V) HYSTCTR S etting 2.5 2.8 3.1 45 ...
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... A small load capacitance (47 pF) can improve the bandwidth performance of the DAC K30 Sub-Family Data Sheet, Rev. 3, 11/2012 1.3 1.6 1.9 2.2 Vin level (V) Min. 1.71 1.13 Operating temperature range of the device — — or the voltage output of the VREF module (VREF_OUT) DDA HYSTCTR Setting 2.5 2.8 3.1 Max. Unit Notes 3 °C 100 Freescale Semiconductor, Inc. ...
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... Calculated by a best fit curve from 3.0 V, reference select set for V DDA 0x800, temperature range is across the full range of the device K30 Sub-Family Data Sheet, Rev. 3, 11/2012. Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Min. Typ. — — — ...
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... Peripheral operating requirements and behaviors Figure 17. Typical INL error vs. digital code K30 Sub-Family Data Sheet, Rev. 3, 11/2012. 48 Freescale Semiconductor, Inc. ...
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... VREF_OUT if the VREF_OUT functionality is being used for either an internal or external L reference. 2. The load capacitance should not exceed +/-25% of the nominal specified C the device. K30 Sub-Family Data Sheet, Rev. 3, 11/2012. Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Min. Max. Unit 1.71 3 ...
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... Min. Max. Unit 0 50 °C Min. Max. Unit 1.173 1.225 V Freescale Semiconductor, Inc. Unit Notes µ µ µ Notes Notes ...
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... The delay is programmable in SPIx_CTARn[PASC] and SPIx_CTARn[ASC]. DSPI_PCSn DS3 DSPI_SCK DS7 (CPOL=0) DSPI_SIN DSPI_SOUT Figure 19. DSPI classic SPI timing — master mode K30 Sub-Family Data Sheet, Rev. 3, 11/2012. Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Min. 2.7 — BUS (t /2) − 2 SCK ( − ...
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... Table continues on the next page... Min. Max. Unit 2.7 3.6 V 12.5 MHz — ns BUS (t /2) − / SCK SCK — — — — ns — — DS9 DS16 DS11 Last data Last data Max. Unit Notes 3 12.5 MHz — ns Freescale Semiconductor, Inc. ...
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... DS13 DSPI_SIN to DSPI_SCK input setup DS14 DSPI_SCK to DSPI_SIN input hold DS15 DSPI_SS active to DSPI_SOUT driven DS16 DSPI_SS inactive to DSPI_SOUT not driven K30 Sub-Family Data Sheet, Rev. 3, 11/2012. Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Min SCK ( − BUS ...
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... This section provides the operating performance over the full operating voltage for the device in Normal Run, Wait and Stop modes. K30 Sub-Family Data Sheet, Rev. 3, 11/2012. 54 DS10 DS15 DS12 First data Data DS14 First data Data DS9 DS16 DS11 Last data Last data Freescale Semiconductor, Inc. ...
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... Table 40. I2S/SAI slave mode timing in Normal Run, Wait and Stop modes (full voltage range) Num. Characteristic Operating voltage S11 I2S_TX_BCLK/I2S_RX_BCLK cycle time (input) S12 I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low (input) K30 Sub-Family Data Sheet, Rev. 3, 11/2012. Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Min. 1.71 40 45% 80 45% — -1.0 — ...
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... S19 S16 S17 S18 Min. 1.71 62.5 45% 250 45% Table continues on the next page... K30 Sub-Family Data Sheet, Rev. 3, 11/2012. Max. Unit — ns — ns — ns — ns — S16 S14 S16 Max. Unit 3.6 V — ns 55% MCLK period — ns 55% BCLK period Freescale Semiconductor, Inc. ...
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... I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low (input) S13 I2S_TX_FS/I2S_RX_FS input setup before I2S_TX_BCLK/I2S_RX_BCLK S14 I2S_TX_FS/I2S_RX_FS input hold after I2S_TX_BCLK/I2S_RX_BCLK S15 I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output valid S16 I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output invalid Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Min. — 0 — ...
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... Table continues on the next page... K30 Sub-Family Data Sheet, Rev. 3, 11/2012. Max. Unit — ns — S16 S14 S16 Typ. Max. Unit Notes — 3 500 MHz 2, 1 1.8 MHz 2, 1 — pF 500 — μ Freescale Semiconductor, Inc ...
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... Frame C LCD charge pump capacitance — nominal value LCD C LCD bypass capacitance — nominal value BYLCD C LCD glass capacitance Glass K30 Sub-Family Data Sheet, Rev. 3, 11/2012. Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Min. Typ. — 2 — 36 — 8.3333 — ...
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... Min. Typ. — — — 1 — 10 — 1 — 0.28 — 2. www.freescale.com and perform a keyword search for Then use this document number 98ASS23308W 98ASA00344D Max. Unit Notes 3 3 IREG — µA 4 — µA — µA — MΩ — MΩ Freescale Semiconductor, Inc. ...
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... ADC1_DP1 J2 17 ADC1_DM1 ADC1_DM1 ADC1_DM1 K1 18 PGA0_DP/ PGA0_DP/ PGA0_DP/ ADC0_DP0/ ADC0_DP0/ ADC0_DP0/ ADC1_DP3 ADC1_DP3 ADC1_DP3 K30 Sub-Family Data Sheet, Rev. 3, 11/2012. Freescale Semiconductor, Inc. ALT1 ALT2 ALT3 ALT4 PTE0 SPI1_PCS1 UART1_TX PTE1/ SPI1_SOUT UART1_RX LLWU_P0 PTE2/ SPI1_SCK UART1_CTS_ LLWU_P1 b PTE3 SPI1_SIN ...
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... UART0_COL_ b PTA1 UART0_RX FTM0_CH6 PTA2 UART0_TX FTM0_CH7 PTA3 UART0_RTS_ FTM0_CH0 b PTA4/ FTM0_CH1 LLWU_P3 PTA5 FTM0_CH2 ALT5 ALT6 ALT7 EzPort EWM_OUT_b EWM_IN RTC_CLKOUT JTAG_TCLK/ EZP_CLK SWD_CLK JTAG_TDI EZP_DI JTAG_TDO/ EZP_DO TRACE_SWO JTAG_TMS/ SWD_DIO NMI_b EZP_CS_b CMP2_OUT I2S0_TX_ JTAG_TRST_ BCLK b Freescale Semiconductor, Inc. ...
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... LCD_P11/ ADC1_SE15 ADC1_SE15 B10 62 PTB16 LCD_P12/ LCD_P12/ TSI0_CH9 TSI0_CH9 E9 63 PTB17 LCD_P13/ LCD_P13/ TSI0_CH10 TSI0_CH10 K30 Sub-Family Data Sheet, Rev. 3, 11/2012. Freescale Semiconductor, Inc. ALT1 ALT2 ALT3 ALT4 PTA12 CAN0_TX FTM1_CH0 PTA13/ CAN0_RX FTM1_CH1 LLWU_P4 PTA14 SPI0_PCS0 UART0_TX PTA15 SPI0_SCK UART0_RX ...
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... ALT7 EzPort FTM2_QD_ LCD_P14 PHA FTM2_QD_ LCD_P15 PHB CMP0_OUT LCD_P16 CMP1_OUT LCD_P17 CMP2_OUT LCD_P18 LCD_P19 I2S0_TXD1 LCD_P20 I2S0_TXD0 LCD_P21 I2S0_TX_FS LCD_P22 CLKOUT I2S0_TX_ LCD_P23 BCLK CMP1_OUT LCD_P24 CMP0_OUT LCD_P25 I2S0_MCLK LCD_P26 LCD_P27 LCD_P28 FTM2_FLT0 LCD_P29 LCD_P30 LCD_P31 LCD_P32 Freescale Semiconductor, Inc. ...
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... — — — — K30 Sub-Family Data Sheet, Rev. 3, 11/2012. Freescale Semiconductor, Inc. ALT1 ALT2 ALT3 ALT4 PTC13 UART4_CTS_ b PTC14 UART4_RX PTC16 UART3_RX PTC17 UART3_TX PTC18 UART3_RTS_ b PTC19 UART3_CTS_ b PTD0/ SPI0_PCS0 UART2_RTS_ LLWU_P12 ...
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... K30 Pinouts The below figure shows the pinout diagram for the devices supported by this document. Many signals may be multiplexed onto a single pin. To determine what signals can be used on which pin, see the previous section. K30 Sub-Family Data Sheet, Rev. 3, 11/2012. 66 Freescale Semiconductor, Inc. ...
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... ADC0_DM1 15 ADC1_DP1 16 ADC1_DM1 17 PGA0_DP/ADC0_DP0/ADC1_DP3 18 PGA0_DM/ADC0_DM0/ADC1_DM3 19 PGA1_DP/ADC1_DP0/ADC0_DP3 20 PGA1_DM/ADC1_DM0/ADC0_DM3 21 VDDA 22 VREFH 23 VREFL 24 VSSA 25 Figure 27. K30 100 LQFP Pinout Diagram K30 Sub-Family Data Sheet, Rev. 3, 11/2012. Freescale Semiconductor, Inc. Pinout 75 VLL3 74 VSS PTC3/LLWU_P7 73 PTC2 72 71 PTC1/LLWU_P6 70 PTC0 PTB23 69 PTB22 68 PTB21 67 66 PTB20 65 PTB19 PTB18 ...
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... Table continues on the next page... VLL1 VLL2 VLL3 A PTC0 PTB16 VCAP2 B PTB19 PTB11 VCAP1 C PTB18 PTB10 PTB8 D PTB17 PTB9 PTB7 E PTB21 PTB20 NC F PTB0/ PTB2 PTB1 G LLWU_P5 PTA3 PTA17 PTA16 RESET_b J PTA14 VSS PTA19 K PTA15 VDD PTA18 Freescale Semiconductor, Inc. ...
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... Updated "I2S/SAI Switching Specifications" section. • Updated "TSI electrical specifications" table. 3 11/2012 • Updated orderable part numbers. • Updated the maximum input voltage (V conditions" section. K30 Sub-Family Data Sheet, Rev. 3, 11/2012. Freescale Semiconductor, Inc. Revision History ) specification in the "16-bit ADC operating ADIN 69 ...
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... Freescale Semiconductor makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any liability, including without limitation consequential or incidental damages. "Typical" parameters that may be provided in Freescale Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time ...