LPC1112FHN24/2021 NXP Semiconductors, LPC1112FHN24/2021 Datasheet - Page 29

• Manufacturer Part Number: LPC1112FHN24/2021
• Description: ARM Microcontrollers - MCU
• Manufacturer: NXP Semiconductors

Specifications of LPC1112FHN24/2021

• Rohs: yes
• Core: ARM Cortex M0
• Processor Series: LPC1112
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 2 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.6 V
• Package / Case: HVQFN-24
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 2450

NXP Semiconductors
Table 8.
[1]
[2]
[3]
[4]
[5]
[6]
Table 9.
LPC111X
Product data sheet
Symbol
PIO3_0/DTR
PIO3_1/DSR
PIO3_2/DCD
PIO3_3/RI
PIO3_4
PIO3_5
V
XTALIN
XTALOUT
V
Symbol
PIO0_0 to PIO0_11
RESET/PIO0_0
DD
SS
Pin state at reset for default function: I = Input; O = Output; PU = internal pull-up enabled (pins pulled up to 2.6 V for
LPC111x/101/201/301, pins pulled up to full V
enabled.
See
reset the chip and wake up from Deep power-down mode. An external pull-up resistor is required on this pin for the Deep power-down
mode.
5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors and configurable hysteresis (see
I
5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors, configurable hysteresis, and analog input.
When configured as a ADC input, digital section of the pad is disabled and the pin is not 5 V tolerant (see
When the system oscillator is not used, connect XTALIN and XTALOUT as follows: XTALIN can be left floating or can be grounded
(grounding is preferred to reduce susceptibility to noise). XTALOUT should be left floating.
2
C-bus pads compliant with the I
Figure 48
LPC1100 and LPC1100L series: LPC1113/14 pin description table (LQFP48 package)
LPC1100 and LPC1100L series: LPC1111/12/13/14 pin description table (HVQFN33 package)
for the reset pad configuration. RESET functionality is not available in Deep power-down mode. Use the WAKEUP pin to
Pin
36
37
43
48
18
21
8; 44
6
7
5; 41
Pin
2
[2]
[6]
[6]
[3]
[3]
[3]
[3]
[3]
[3]
Start
logic
input
yes
Start
logic
input
no
no
no
no
no
no
-
-
-
-
2
C-bus specification for I
Type Reset
I
I/O
Type
I/O
O
I/O
I
I/O
I
I/O
I
I/O
I/O
I
I
O
I
All information provided in this document is subject to legal disclaimers.
DD
state
[1]
I;PU
-
level on LPC111x/002/102/202/302 (V
Rev. 8 — 20 February 2013
Reset
state
[1]
I; PU
-
I; PU
-
I; PU
-
I; PU
-
I; PU
I; PU
-
-
-
-
Description
Port 0 — Port 0 is a 12-bit I/O port with individual direction and
function controls for each bit. The operation of port 0 pins depends on
the function selected through the IOCONFIG register block.
RESET — External reset input with 20 ns glitch filter. A LOW-going
pulse as short as 50 ns on this pin resets the device, causing I/O ports
and peripherals to take on their default states and processor execution
to begin at address 0.
PIO0_0 — General purpose digital input/output pin with 10 ns glitch
filter.
2
C standard mode and I
Description
PIO3_0 — General purpose digital input/output pin.
DTR — Data Terminal Ready output for UART.
PIO3_1 — General purpose digital input/output pin.
DSR — Data Set Ready input for UART.
PIO3_2 — General purpose digital input/output pin.
DCD — Data Carrier Detect input for UART.
PIO3_3 — General purpose digital input/output pin.
RI — Ring Indicator input for UART.
PIO3_4 — General purpose digital input/output pin.
PIO3_5 — General purpose digital input/output pin.
3.3 V supply voltage to the internal regulator, the external rail,
and the ADC. Also used as the ADC reference voltage.
Input to the oscillator circuit and internal clock generator circuits.
Input voltage must not exceed 1.8 V.
Output from the oscillator amplifier.
Ground.
LPC1110/11/12/13/14/15
2
C Fast-mode Plus.
32-bit ARM Cortex-M0 microcontroller
DD
= 3.3 V)); IA = inactive, no pull-up/down
Figure
…continued
© NXP B.V. 2013. All rights reserved.
47).
Figure
29 of 114
47).