MAX5290BEUD Maxim Integrated, MAX5290BEUD Datasheet
MAX5290BEUD
Specifications of MAX5290BEUD
Related parts for MAX5290BEUD
MAX5290BEUD Summary of contents
Page 1
... AV ♦ 20MHz 3-Wire SPI-/QSPI-/MICROWIRE- and DSP-Compatible Serial Interface ♦ Glitch-Free Outputs Power Up to Zero Scale, Midscale or Full Scale ♦ Unity-Gain- or Force-Sense-Configured Output Buffers Applications PART MAX5290AEUD MAX5290BEUD MAX5290AETE* MAX5290BETE* MAX5291AEUE MAX5291BEUE MAX5291AETE* MAX5291BETE* MAX5292EUD MAX5292ETE* MAX5293EUE MAX5293ETE* ...
Page 2
Buffered, Fast-Settling, Dual, 12-/10-/8-Bit, Voltage-Output DACs ABSOLUTE MAXIMUM RATINGS ........................................................................± AGND to DGND ..................................................................±0. AGND, DGND.............................................-0. AGND, DGND ............................................-0.3V to +6V DD FB_, OUT_, REF to AGND ........-0.3V ...
Page 3
Buffered, Fast-Settling, Dual, 12-/10-/8-Bit, ELECTRICAL CHARACTERISTICS (continued) (AV = 2.7V to 5.25V 1. unless otherwise noted. Typical values are at T PARAMETER SYMBOL Power-Supply Rejection PSRR Ratio REFERENCE INPUT Reference Input Range V REF ...
Page 4
Buffered, Fast-Settling, Dual, 12-/10-/8-Bit, Voltage-Output DACs ELECTRICAL CHARACTERISTICS (continued) (AV = 2.7V to 5.25V 1. unless otherwise noted. Typical values are at T PARAMETER SYMBOL PU INPUT Input High Voltage V IH-PU Input Low ...
Page 5
Buffered, Fast-Settling, Dual, 12-/10-/8-Bit, ELECTRICAL CHARACTERISTICS (continued) (AV = 2.7V to 5.25V 1. unless otherwise noted. Typical values are at T PARAMETER SYMBOL POWER REQUIREMENTS Analog Supply Voltage AV DD Range Digital Supply Voltage ...
Page 6
Buffered, Fast-Settling, Dual, 12-/10-/8-Bit, Voltage-Output DACs TIMING CHARACTERISTICS—DSP Mode Disabled (3V, 3.3V Logic) (Figure 1) (continued) ( 2.7V to 5.25V, DGND = MIN to T MAX , unless otherwise noted.) PARAMETER SYMBOL UPIO ...
Page 7
Buffered, Fast-Settling, Dual, 12-/10-/8-Bit, TIMING CHARACTERISTICS—DSP Mode Disabled (1.8V Logic) (Figure 1) (continued) ( 1.8V to 5.25V, DGND = MIN to T MAX , unless otherwise noted.) PARAMETER SYMBOL UPIO_ TIMING CHARACTERISTICS DOUT ...
Page 8
Buffered, Fast-Settling, Dual, 12-/10-/8-Bit, Voltage-Output DACs TIMING CHARACTERISTICS—DSP Mode Enabled (3V, 3.3V Logic) (Figure 2) (continued) ( 2.7V to 5.25V, DGND = MIN to T MAX , unless otherwise noted.) PARAMETER SYMBOL UPIO_ ...
Page 9
Buffered, Fast-Settling, Dual, 12-/10-/8-Bit, TIMING CHARACTERISTICS—DSP Mode Enabled (1.8V Logic) (Figure 2) (continued) ( 1.8V to 5.25V, DGND = MIN to T MAX , unless otherwise noted.) PARAMETER SYMBOL UPIO_ TIMING CHARACTERISTICS DOUT ...
Page 10
Buffered, Fast-Settling, Dual, 12-/10-/8-Bit, Voltage-Output DACs ( 3V 2.5V 10kΩ REF L INTEGRAL NONLINEARITY vs. DIGITAL INPUT CODE (MAX5290A) 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 0 1000 2000 3000 ...
Page 11
Buffered, Fast-Settling, Dual, 12-/10-/8-Bit 2.5V 10kΩ REF L INTEGRAL NONLINEARITY vs. TEMPERATURE (12-BIT) 4 UNITY GAIN B-GRADE -40 - TEMPERATURE (°C) ...
Page 12
Buffered, Fast-Settling, Dual, 12-/10-/8-Bit, Voltage-Output DACs (T = +25°C, unless otherwise noted.) A SUPPLY CURRENT vs. DIGITAL INPUT CODE (FORCE SENSE) 1.2 1.1 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 SLOW MODE 0.2 12-BIT 0.1 NO LOAD 0 0 ...
Page 13
Buffered, Fast-Settling, Dual, 12-/10-/8-Bit +25°C, unless otherwise noted.) A SETTLING TIME POSITIVE MAX5290 toc28 FULL-SCALE TRANSITION OUT_ 2V/div CS 2V/div 400ns/div REFERENCE FEEDTHROUGH AT 1kHz -22 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -142 ...
Page 14
Buffered, Fast-Settling, Dual, 12-/10-/8-Bit, Voltage-Output DACs PIN MAX5290 MAX5291 MAX5292 MAX5293 MAX5294 MAX5295 THIN QFN TSSOP THIN QFN ...
Page 15
Buffered, Fast-Settling, Dual, 12-/10-/8-Bit, CS SERIAL SCLK INTERFACE CONTROL DIN DSP 16-BIT SHIFT REGISTER UPIO1 UPIO1 AND UPIO2 UPIO2 LOGIC DECODE CONTROL PU REF ______________________________________________________________________________________ Voltage-Output DACs AV DV AGND DD DD POWER-DOWN LOGIC AND REGISTER INPUT DAC REGISTER REGISTER ...
Page 16
Buffered, Fast-Settling, Dual, 12-/10-/8-Bit, Voltage-Output DACs CS SERIAL INTERFACE SCLK CONTROL DIN DSP 16-BIT SHIFT REGISTER UPIO1 UPIO1 AND UPIO2 UPIO2 LOGIC DECODE CONTROL PU REF 16 ______________________________________________________________________________________ Functional Diagrams (continued AGND DGND DD DD POWER-DOWN LOGIC AND ...
Page 17
Buffered, Fast-Settling, Dual, 12-/10-/8-Bit, Detailed Description The MAX5290–MAX5295 dual, 12-/10-/8-bit, voltage- output digital-to-analog converters (DACs) offer buffered outputs and a 3µs maximum settling time at the 12-bit level. The DACs operate from a single 2.7V to 5.25V analog supply and ...
Page 18
Buffered, Fast-Settling, Dual, 12-/10-/8-Bit, Voltage-Output DACs Table 1. Serial Write Data Format MSB CONTROL BITS D11 SCLK DIN CS t CSW DOUTDC1* DOUTDC0 OR DOUTRB* *UPIO1/UPIO2 CONFIGURED AS DOUTDC_ (DAISY-CHAIN DATA OUTPUT, MODE ...
Page 19
Buffered, Fast-Settling, Dual, 12-/10-/8-Bit, Serial-Interface Programming Commands Tables 2a, 2b, and 2c provide all of the serial-interface programming commands for the MAX5290–MAX5295. Table 2a shows the basic DAC programming com- mands, Table 2b gives the advanced-feature program- ming commands, and ...
Page 20
Buffered, Fast-Settling, Dual, 12-/10-/8-Bit, Voltage-Output DACs 20 ______________________________________________________________________________________ ...
Page 21
Buffered, Fast-Settling, Dual, 12-/10-/8-Bit, ______________________________________________________________________________________ Voltage-Output DACs 21 ...
Page 22
Buffered, Fast-Settling, Dual, 12-/10-/8-Bit, Voltage-Output DACs 22 ______________________________________________________________________________________ ...
Page 23
Buffered, Fast-Settling, Dual, 12-/10-/8-Bit, Default register values at power-up correspond to the state of PU, e.g. input and DAC registers are set to 800hex floating, FFFhex 000hex if PU= DGND. DAC Programming Examples: ...
Page 24
Buffered, Fast-Settling, Dual, 12-/10-/8-Bit, Voltage-Output DACs Select Bits Programming Example: To load DAC register B from input register B while keeping channel A unchanged, set and the command in Table 7. Table ...
Page 25
Buffered, Fast-Settling, Dual, 12-/10-/8-Bit, Settling-Time-Mode Bits (SPDA, SPDB) The settling-time-mode bits select the settling time (FAST mode or SLOW mode) of the MAX5290– MAX5295. Set SPD_ = 1 to select FAST mode or set SPD_ = 0 to select SLOW ...
Page 26
Buffered, Fast-Settling, Dual, 12-/10-/8-Bit, Voltage-Output DACs and CPHA = 1 or set CPOL = 1 and CPHA = 0 for DSP and SPI applications requiring the clocking of data in on the falling edge of SCLK (refer to the Programmer’s ...
Page 27
Buffered, Fast-Settling, Dual, 12-/10-/8-Bit, User-Programmable Input/Output (UPIO) Table 22 lists the possible configurations for UPIO1 and UPIO2. UPIO1 and UPIO2 use the selected function when configured by the UP3–UP0 configuration bits. LDAC controls loading of the DAC registers. When LDAC ...
Page 28
Buffered, Fast-Settling, Dual, 12-/10-/8-Bit, Voltage-Output DACs The SET, MID, and CLR signals force the DAC outputs to full scale, midscale, or zero scale (Figure 5). These signals cannot be active at the same time. The active-low SET input forces the ...
Page 29
Buffered, Fast-Settling, Dual, 12-/10-/8-Bit, UPIO1 and UPIO2 can each be configured as a gener- al-purpose logic input (GPI), a general-purpose logic- low output (GPOL), or general-purpose logic-high output (GPOH). The GPI can detect interrupts from µPs or microcon- trollers. It ...
Page 30
Buffered, Fast-Settling, Dual, 12-/10-/8-Bit, Voltage-Output DACs Applications Information Figure 7 shows the unity gain of the MAX5290 in a unipolar output configuration. Table 24 lists the unipolar output codes. The MAX5290 outputs can be configured for bipolar operation, as shown ...
Page 31
Buffered, Fast-Settling, Dual, 12-/10-/8-Bit, Power-Supply and Layout Considerations Bypass the analog and digital power supplies with a 10µF capacitor in parallel with a 0.1µF capacitor to ana- log ground (AGND) and digital ground (DGND) (see Figure 10). Minimize lead lengths ...
Page 32
... SCLK (4mm x 4mm) THIN QFN Selector Guide OUTPUT R ESO L U TIO N BUFFER PART CO NFIGUR ATION MAX5290AEUD Unity Gain MAX5290BEUD Unity Gain MAX5290AETE* Unity Gain MAX5290BETE Unity Gain MAX5291AEUE Force Sense MAX5291BEUE Force Sense MAX5291AETE* Force Sense MAX5291BETE Force Sense ...
Page 33
Buffered, Fast-Settling, Dual, 12-/10-/8-Bit, (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.) ______________________________________________________________________________________ Voltage-Output DACs Package Information PACKAGE OUTLINE, TSSOP 4.40mm BODY 21-0066 1 I ...
Page 34
Buffered, Fast-Settling, Dual, 12-/10-/8-Bit, Voltage-Output DACs (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.) 34 ______________________________________________________________________________________ Package Information (continued) PACKAGE OUTLINE, 12, 16, 20, 24, ...
Page 35
... Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 35 © 2007 Maxim Integrated Products ...