MAX5290BEUD Maxim Integrated, MAX5290BEUD Datasheet - Page 25

• Manufacturer Part Number: MAX5290BEUD
• Description: Digital to Analog Converters - DAC
• Manufacturer: Maxim Integrated

Specifications of MAX5290BEUD

• Number Of Converters: 2
• Number Of Dac Outputs: 2
• Resolution: 12 bit
• Interface Type: QSPI, SPI, Serial (3-Wire, Microwire)
• Settling Time: 6 us
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: TSSOP-14
• Minimum Operating Temperature: - 40 C
• Output Type: Voltage
• Supply Voltage - Max: 5.25 V
• Supply Voltage - Min: 2.7 V
• Voltage Reference: External

The settling-time-mode bits select the settling time
(FAST mode or SLOW mode) of the MAX5290–
MAX5295. Set SPD_ = 1 to select FAST mode or set
SPD_ = 0 to select SLOW mode, where “_” is replaced
by A or B, depending on the selected channel (see
Table 12). FAST mode provides a 3µs maximum set-
tling time and SLOW mode provides a 10µs maximum
settling time. Default settling-time mode bits are [0, 0]
(SLOW mode for both DACs).
Table 13. Settling-Time-Mode Write Example
X = Don’t care.
Table 14. Settling-Time-Mode Read Command
X = Don’t care.
Table 15. CPOL and CPHA Bits
Table 16. CPOL and CPHA Write Command
X = Don’t care.
Table 17. CPOL and CPHA Read Command
X = Don’t care.
DATA
DATA
DOUTRB
DOUTRB
DIN
DIN
DATA
DATA
CPOL
DIN
DIN
0
0
1
1
1
1
CONTROL BITS
CONTROL BITS
1
X
X
1
1
1
CONTROL BITS
Settling-Time-Mode Bits (SPDA, SPDB)
Buffered, Fast-Settling, Dual, 12-/10-/8-Bit,
CPHA
CONTROL BITS
1
X
0
1
0
1
______________________________________________________________________________________
1
1
X
1
X
1
1
0
X
1
Default values at power-up when DSP is connected to DV
of SCLK.
Default values at power-up when DSP is connected to DGND. Data is clocked in on the falling edge
of SCLK.
Data is clocked in on the falling edge of SCLK.
Data is clocked in on the rising edge of SCLK.
X
1
0
1
0
X
0
X
1
0
X
1
X
0
0
0
1
X
0
X
X
1
X
0
X
1
X
X
X
X
Settling-Time-Mode Write Example:
To configure DACA into FAST mode and DACB into
SLOW mode, use the command in Table 13.
To read back the settling-time-mode bits, use the com-
mand in Table 14.
The
MAX5290–MAX5295 are defined the same as the CPOL
and CPHA bits in the SPI standard. Set the CPOL = 0
and CPHA = 0 or set CPOL = 1 and CPHA = 1 for
MICROWIRE and SPI applications requiring the clocking
of data in on the rising edge of SCLK. Set the CPOL = 0
X
X
X
X
DESCRIPTION
Voltage-Output DACs
DATA BITS
DATA BITS
X
CPOL
X
DATA BITS
X
X
X
X
DATA BITS
X
X
and
X
X
DD
X
X
. Data is clocked in on the rising edge
X
X
CPHA
X
X
X
X
CPOL and CPHA Control Bits
X
X
X
X
X
X
control
X
X
X
X
X
X
SPDB
bits
CPOL
CPOL CPHA
X
0
X
of
SPDA
CPHA
X
1
X
the
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