MAX5290BEUD Maxim Integrated, MAX5290BEUD Datasheet - Page 28

• Manufacturer Part Number: MAX5290BEUD
• Description: Digital to Analog Converters - DAC
• Manufacturer: Maxim Integrated

Specifications of MAX5290BEUD

• Number Of Converters: 2
• Number Of Dac Outputs: 2
• Resolution: 12 bit
• Interface Type: QSPI, SPI, Serial (3-Wire, Microwire)
• Settling Time: 6 us
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: TSSOP-14
• Minimum Operating Temperature: - 40 C
• Output Type: Voltage
• Supply Voltage - Max: 5.25 V
• Supply Voltage - Min: 2.7 V
• Voltage Reference: External

The SET, MID, and CLR signals force the DAC outputs
to full scale, midscale, or zero scale (Figure 5). These
signals cannot be active at the same time.
The active-low SET input forces the DAC outputs to full
scale when SET is low. When SET is high, the DAC out-
puts follow the data in the DAC registers.
The active-low MID input forces the DAC outputs to mid-
scale when MID is low. When MID is high, the DAC out-
puts follow the data in the DAC registers.
The active-low CLR input forces the DAC outputs to zero
scale when CLR is low. When CLR is high, the DAC out-
puts follow the data in the DAC registers.
If CLR, MID, or SET signals go low in the middle of a write
command, reload the data to ensure accurate results.
The PDL active-low software-shutdown lockout input
overrides (not overwrites), the PD_0 and PD_1 shut-
down mode bits. PDL cannot be active at the same
time as SHDN1K or SHDN100K (see the Shutdown
Mode ( SHDN1K , SHDN100K ) section).
If the PD_0 and PD_1 bits command the DAC to shut
down prior to PDL going low, the DAC returns to shut-
down mode immediately after PDL goes high, unless
the PD_0 and PD_1 bits are changed in the meantime.
The SHDN1K and SHDN100K are active-low signals
that override (not overwrite) the PD_1 and PD_0 bit set-
tings. For the MAX5290/MAX5292/MAX5294, drive
SHDN1K low to select shutdown mode with OUTA and
OUTB internally terminated with 1kΩ to ground, or drive
SHDN100K low to select shutdown with an internal
100kΩ termination. For the MAX5291/MAX5293/
MAX5295, drive SHDN1K low for shutdown with 1kΩ
output termination, or drive SHDN100K low for shut-
down with high-impedance outputs.
UPIO1 and UPIO2 can be configured as serial data
outputs, DOUTRB (data out for read back), DOUTDC0
(data out for daisy-chaining, mode 0), and DOUTDC1
(data out for daisy-chaining, mode 1). The differences
between DOUTRB and DOUTDC0 (or DOUTDC1) are
as follows:
Buffered, Fast-Settling, Dual, 12-/10-/8-Bit,
Voltage-Output DACs
28
______________________________________________________________________________________
Data Output (DOUTRB, DOUTDC0, DOUTDC1)
Shutdown Mode ( S S H H D D N N 1 1 K K , S S H H D D N N 1 1 0 0 0 0 K K )
Power-Down Lockout ( PDL )
SET
, MID , CLR
• The source of read-back data on DOUTRB is the
• Read-back data on DOUTRB is only present after a
• The DOUTRB idle state (CS = high) for read back is
See Figures 1 and 2 for timing details.
Figure 5. Asynchronous Signal Timing
Figure 6. GPO_ and LDAC Signal Timing
MID, OR
V
TOGG
LDAC
CYCLE*
END OF
DOUT register. Daisy-chain DOUTDC_ data comes
directly from the shift register.
DAC read command. Daisy-chain data is present on
DOUTDC_ for any DAC write after the first 16 bits
are written.
high impedance. Daisy-chain DOUTDC_ idles high
when inactive to avoid floating the data input in the
next device in the daisy-chain.
CLR,
OUT_
PDL AFFECTS DAC OUPTUTS (V
PDL
SET
GPO_
LDAC
*END-OF-CYCLE REPRESENTS THE RISING EDGE OF CS OR THE 16TH
ACTIVE CLOCK EDGE, DEPENDING ON THE MODE OF OPERATION.
t
LDS
OUT_
t
t
CMS
LDL
) ONLY IF DACS WERE PREVIOUSLY SHUT DOWN.
t
GP
t
S
±0.5 LSB