MAX5290BEUD Maxim Integrated, MAX5290BEUD Datasheet - Page 7

• Manufacturer Part Number: MAX5290BEUD
• Description: Digital to Analog Converters - DAC
• Manufacturer: Maxim Integrated

Specifications of MAX5290BEUD

• Number Of Converters: 2
• Number Of Dac Outputs: 2
• Resolution: 12 bit
• Interface Type: QSPI, SPI, Serial (3-Wire, Microwire)
• Settling Time: 6 us
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: TSSOP-14
• Minimum Operating Temperature: - 40 C
• Output Type: Voltage
• Supply Voltage - Max: 5.25 V
• Supply Voltage - Min: 2.7 V
• Voltage Reference: External

TIMING CHARACTERISTICS—DSP Mode Disabled (1.8V Logic) (Figure 1) (continued)
(DV DD = 1.8V to 5.25V, DGND = 0, T A = T MIN to T MAX , unless otherwise noted.)
TIMING CHARACTERISTICS—DSP Mode Enabled (3V, 3.3V Logic) (Figure 2)
(DV DD = 2.7V to 5.25V, DGND = 0, T A = T MIN to T MAX , unless otherwise noted.)
UPIO_ TIMING CHARACTERISTICS
DOUT Tri-State Time when
Exiting DOUTDC0, DOUTDC1, or
DOUTRB UPIO Modes
DOUTRB Tri-State Time from CS
Rise
DOUTRB Tri-State Enable Time
from 8th SCLK Rise
LDAC Pulse-Width Low
LDAC Effective Delay
CLR, MID, SET Pulse-Width Low
GPO Output Settling Time
GPO Output High-Impedance
Time
SCLK Frequency
SCLK Pulse-Width High
SCLK Pulse-Width Low
CS Fall to SCLK Fall Setup Time
DSP Fall to SCLK Fall Setup Time
SCLK Fall to CS Rise Hold Time
SCLK Fall to CS Fall Delay
SCLK Fall to DSP Fall Delay
DIN to SCLK Fall Setup Time
DIN to SCLK Fall Hold Time
SCLK Rise to DOUT_ Valid
Propagation Delay
SCLK Fall to DOUTDC0 Valid
Propagation Delay
CS Rise to SCLK Fall Hold Time
CS Pulse-Width High
DSP Pulse-Width High
DSP Pulse-Width Low
PARAMETER
PARAMETER
Buffered, Fast-Settling, Dual, 12-/10-/8-Bit,
_______________________________________________________________________________________
SYMBOL
SYMBOL
t
t
DSPWL
f
t
t
t
t
DRBZ
t
t
t
t
t
t
t
SCLK
t
t
t
t
t
DOZ
CMS
CSW
DSW
ZEN
t
GPZ
t
CSH
t
DO1
DO2
LDL
LDS
t
CSS
DSS
CS0
DS0
t
CS1
GP
CH
DH
CL
DS
C
in high impedance
C
in high impedance
C
UPIO_ driven out of tri-state
Figure 5
Figure 6
Figure 5
Figure 6
2.7V < DV
(Note 7)
(Note 7)
C
mode
C
MICROWIRE and SPI modes 0 and 3
(Note 8)
L
L
L
L
L
= 20pF, from end of write cycle to UPIO_
= 20pF, from rising edge of CS to UPIO_
= 20pF, from 8th rising edge of SCLK to
= 20pF, UPIO_ = DOUTDC1 or DOUTRB
= 20pF, UPIO_ = DOUTDC0 mode
DD
< 5.25V
CONDITIONS
CONDITIONS
Voltage-Output DACs
MIN
MIN
200
40
40
20
20
10
10
10
10
12
10
45
20
20
0
5
5
TYP
TYP
MAX
MAX
200
200
200
40
20
30
30
UNITS
UNITS
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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