LCMXO2-1200HC-4TG144I Lattice, LCMXO2-1200HC-4TG144I Datasheet - Page 103
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LCMXO2-1200HC-4TG144I
Manufacturer Part Number
LCMXO2-1200HC-4TG144I
Description
FPGA - Field Programmable Gate Array 1280 LUTs 108 I/O 3.3V -4 SPD
Manufacturer
Lattice
Datasheet
1.LCMXO2-256HC-4SG32I.pdf
(106 pages)
Specifications of LCMXO2-1200HC-4TG144I
Rohs
yes
Number Of Gates
1.2 K
Embedded Block Ram - Ebr
64 Kbit
Number Of I/os
108
Maximum Operating Frequency
269 MHz
Operating Supply Voltage
1.14 V to 3.465 V, 2.375 V to 3.465 V
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Package / Case
TQFP-144
Distributed Ram
10 Kbit
Minimum Operating Temperature
- 40 C
Operating Supply Current
3.49 mA
Factory Pack Quantity
60
User Flash Memory - Ufm
64 Kbit
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LCMXO2-1200HC-4TG144I
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
Part Number:
LCMXO2-1200HC-4TG144I
Manufacturer:
LATTICE
Quantity:
20 000
Company:
Part Number:
LCMXO2-1200HC-4TG144IR1
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
www.latticesemi.com
© 2012 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
April 2012
For Further Information
A variety of technical notes for the MachXO2 family are available on the Lattice web site.
• TN1198,
• TN1199,
• TN1201,
• TN1202,
• TN1203,
• TN1204,
• TN1205,
• TN1206,
• TN1207,
• TN1074,
• TN1087,
• AN8086,
• AN8066,
•
•
•
For further information on interface standards, refer to the following web sites:
• JEDEC Standards (LVTTL, LVCMOS, LVDS, DDR, DDR2, LPDDR):
• PCI:
MachXO2 Device Pinout Files
Thermal Management
Lattice design tools
www.pcisig.com
Power Estimation and Management for MachXO2 Devices
MachXO2 sysCLOCK PLL Design and Usage Guide
Memory Usage Guide for MachXO2 Devices
MachXO2 sysIO Usage Guide
Implementing High-Speed Interfaces with MachXO2 Devices
MachXO2 Programming and Configuration Usage Guide
Using User Flash Memory and Hardened Control Functions in MachXO2 Devices
MachXO2 SRAM CRC Error Detection Usage Guide
Using TraceID in MachXO2 Devices
PCB Layout Recommendations for BGA Packages
Minimizing System Interruption During Configuration Using TransFR Technology
Designing for Migration from MachXO2-1200-R1 to Standard (non-R1) Devices
Boundary Scan Testability with Lattice sysIO Capability
document
MachXO2 Family Data Sheet
6-1
Supplemental Information
www.jedec.org
DS1035
Data Sheet DS1035
Further Info_01.3