LCMXO2-1200HC-4TG144I Lattice, LCMXO2-1200HC-4TG144I Datasheet - Page 2
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LCMXO2-1200HC-4TG144I
Manufacturer Part Number
LCMXO2-1200HC-4TG144I
Description
FPGA - Field Programmable Gate Array 1280 LUTs 108 I/O 3.3V -4 SPD
Manufacturer
Lattice
Datasheet
1.LCMXO2-256HC-4SG32I.pdf
(106 pages)
Specifications of LCMXO2-1200HC-4TG144I
Rohs
yes
Number Of Gates
1.2 K
Embedded Block Ram - Ebr
64 Kbit
Number Of I/os
108
Maximum Operating Frequency
269 MHz
Operating Supply Voltage
1.14 V to 3.465 V, 2.375 V to 3.465 V
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Package / Case
TQFP-144
Distributed Ram
10 Kbit
Minimum Operating Temperature
- 40 C
Operating Supply Current
3.49 mA
Factory Pack Quantity
60
User Flash Memory - Ufm
64 Kbit
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LCMXO2-1200HC-4TG144I
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
Part Number:
LCMXO2-1200HC-4TG144I
Manufacturer:
LATTICE
Quantity:
20 000
Company:
Part Number:
LCMXO2-1200HC-4TG144IR1
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
January 2013
Features
Flexible Logic Architecture
Ultra Low Power Devices
Embedded and Distributed Memory
On-Chip User Flash Memory
Pre-Engineered Source Synchronous I/O
High Performance, Flexible I/O Buffer
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or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
www.latticesemi.com
• Six devices with 256 to 6864 LUT4s and
• Advanced 65 nm low power process
• As low as 19 µW standby power
• Programmable low swing differential I/Os
• Stand-by mode and other power saving options
• Up to 240 Kbits sysMEM™ Embedded Block
• Up to 54 Kbits Distributed RAM
• Dedicated FIFO control logic
• Up to 256 Kbits of User Flash Memory
• 100,000 write cycles
• Accessible through WISHBONE, SPI, I
• Can be used as soft processor PROM or as
• DDR registers in I/O cells
• Dedicated gearing logic
• 7:1 Gearing for Display I/Os
• Generic DDR, DDRX2, DDRX4
• Dedicated DDR/DDR2/LPDDR memory with
• Programmable sysIO™ buffer supports wide
• I/Os support hot socketing
• On-chip differential termination
• Programmable pull-up or pull-down mode
19 to 335 I/Os
RAM
JTAG interfaces
Flash memory
DQS support
range of interfaces:
– LVCMOS 3.3/2.5/1.8/1.5/1.2
– LVTTL
– PCI
– LVDS, Bus-LVDS, MLVDS, RSDS, LVPECL
– SSTL 25/18
– HSTL 18
– Schmitt trigger inputs, up to 0.5V hysteresis
2
C and
MachXO2 Family Data Sheet
1-1
Flexible On-Chip Clocking
Non-volatile, Infinitely Reconfigurable
TransFR™ Reconfiguration
Enhanced System Level Support
Broad Range of Package Options
• Eight primary clocks
• Up to two edge clocks for high-speed I/O
• Up to two analog PLLs per device with
• Instant-on – powers up in microseconds
• Single-chip, secure solution
• Programmable through JTAG, SPI or I
• Supports background programming of non-vola-
• Optional dual boot with external SPI memory
• In-field logic update while system operates
• On-chip hardened functions: SPI, I
• On-chip oscillator with 5.5% accuracy
• Unique TraceID for system tracking
• One Time Programmable (OTP) mode
• Single power supply with extended operating
• IEEE Standard 1149.1 boundary scan
• IEEE 1532 compliant in-system programming
• TQFP, WLCSP, ucBGA, csBGA, caBGA, ftBGA,
• Small footprint package options
• Density migration supported
• Advanced halogen-free packaging
interfaces (top and bottom sides only)
fractional-n frequency synthesis
tile memory
counter
range
fpBGA, QFN package options
– Wide input frequency range (10 MHz to
– As small as 2.5x2.5mm
400 MHz)
Introduction
DS1035
Data Sheet DS1035
Introduction_01.6
2
C, timer/
2
C