LCMXO2-1200HC-4TG144I Lattice, LCMXO2-1200HC-4TG144I Datasheet - Page 23
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LCMXO2-1200HC-4TG144I
Manufacturer Part Number
LCMXO2-1200HC-4TG144I
Description
FPGA - Field Programmable Gate Array 1280 LUTs 108 I/O 3.3V -4 SPD
Manufacturer
Lattice
Datasheet
1.LCMXO2-256HC-4SG32I.pdf
(106 pages)
Specifications of LCMXO2-1200HC-4TG144I
Rohs
yes
Number Of Gates
1.2 K
Embedded Block Ram - Ebr
64 Kbit
Number Of I/os
108
Maximum Operating Frequency
269 MHz
Operating Supply Voltage
1.14 V to 3.465 V, 2.375 V to 3.465 V
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Package / Case
TQFP-144
Distributed Ram
10 Kbit
Minimum Operating Temperature
- 40 C
Operating Supply Current
3.49 mA
Factory Pack Quantity
60
User Flash Memory - Ufm
64 Kbit
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LCMXO2-1200HC-4TG144I
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
Part Number:
LCMXO2-1200HC-4TG144I
Manufacturer:
LATTICE
Quantity:
20 000
Company:
Part Number:
LCMXO2-1200HC-4TG144IR1
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
These gearboxes have three stage pipeline registers. The first stage registers sample the high-speed input data by
the high-speed edge clock on its rising and falling edges. The second stage registers perform data alignment
based on the control signals UPDATE and SEL0 from the control block. The third stage pipeline registers pass the
data to the device core synchronized to the low-speed system clock. Figure 2-16 shows a block diagram of the
input gearbox.
Figure 2-16. Input Gearbox
D
ECLK0/1
UPDATE
SEL0
Q21
Q43
Q65
Q_6
Q32
Q54
D Q
D Q
D Q
D Q
D Q
D Q
D Q
D Q
cdn
Q0_
Q21
Q43
Q65
Q_6
Q54
Q32
Q10
Q10
Q32
Q54
Q_6
Q21
Q43
Q65
2-19
CE
D Q
CE
CE
CE
CE
CE
CE
CE
D Q
D Q
D Q
D Q
D Q
D Q
D Q
cdn
S1
S0
S2
S4
S6
S7
S5
S3
D Q
D Q
D Q
D Q
D Q
MachXO2 Family Data Sheet
D
D
D
T0
T2
T4
T6
T5
T3
T1
T7
Q0
Q2
Q4
Q6
Q7
Q5
Q3
Q1
SCLK
Architecture