LCMXO2-1200HC-4TG144I Lattice, LCMXO2-1200HC-4TG144I Datasheet - Page 35
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LCMXO2-1200HC-4TG144I
Manufacturer Part Number
LCMXO2-1200HC-4TG144I
Description
FPGA - Field Programmable Gate Array 1280 LUTs 108 I/O 3.3V -4 SPD
Manufacturer
Lattice
Datasheet
1.LCMXO2-256HC-4SG32I.pdf
(106 pages)
Specifications of LCMXO2-1200HC-4TG144I
Rohs
yes
Number Of Gates
1.2 K
Embedded Block Ram - Ebr
64 Kbit
Number Of I/os
108
Maximum Operating Frequency
269 MHz
Operating Supply Voltage
1.14 V to 3.465 V, 2.375 V to 3.465 V
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Package / Case
TQFP-144
Distributed Ram
10 Kbit
Minimum Operating Temperature
- 40 C
Operating Supply Current
3.49 mA
Factory Pack Quantity
60
User Flash Memory - Ufm
64 Kbit
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LCMXO2-1200HC-4TG144I
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
Part Number:
LCMXO2-1200HC-4TG144I
Manufacturer:
LATTICE
Quantity:
20 000
Company:
Part Number:
LCMXO2-1200HC-4TG144IR1
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
Figure 2-23. Timer/Counter Block Diagram
Table 2-17. Timer/Counter Signal Description
For more details on these embedded functions, please refer to TN1205,
Control Functions in MachXO2
tc_clki
tc_rstn
tc_ic
tc_int
tc_oc
• Supports the following modes of operation:
• Programmable clock input source
• Programmable input clock prescaler
• One static interrupt output to routing
• One wake-up interrupt to on-chip standby mode controller.
• Three independent interrupt sources: overflow, output compare match, and input capture
• Auto reload
• Time-stamping support on the input capture unit
• Waveform generation on the output
• Glitch-free PWM waveform generation with variable PWM period
• Internal WISHBONE bus access to the control and status registers
• Stand-alone mode with preloaded control registers and direct reset input
– Watchdog timer
– Clear timer on compare match
– Fast PWM
– Phase and Frequency Correct PWM
Port
Routing
I/O
Logic
O
O
Core
I
I
I
Timer/Counter input clock signal
Register tc_rstn_ena is preloaded by configuration to always keep this pin enabled
Input capture trigger event, applicable for non-pwm modes with WISHBONE interface. If
enabled, a rising edge of this signal will be detected and synchronized to capture tc_cnt value
into tc_icr for time-stamping.
Without WISHBONE – Can be used as overflow flag
With WISHBONE – Controlled by three IRQ registers
Timer counter output signal
Devices.
EFB
WISHBONE
Interface
EFB
Registers
Counter
Timer/
2-31
Description
Timer/Counter
Control
Logic
Using User Flash Memory and Hardened
MachXO2 Family Data Sheet
PWM
Architecture