iCE40LP1K-CM36TR Lattice, iCE40LP1K-CM36TR Datasheet - Page 3

• Manufacturer Part Number: iCE40LP1K-CM36TR
• Description: FPGA - Field Programmable Gate Array iCE40LP 1280 LUTs, 1.2V Ultra Low-Power
• Manufacturer: Lattice

Specifications of iCE40LP1K-CM36TR

• Rohs: yes

Table 1-1. iCE40 Family Selection Guide (Cont.)
Introduction
The iCE40 family of ultra-low power, non-volatile FPGAs has four devices with densities ranging from 384 to 7680
Look-Up Tables (LUTs). In addition to LUT-based, low-cost programmable logic, these devices feature Embedded
Block RAM (EBR), Non-volatile Configuration Memory (NVCM) and Phase Locked Loops (PLLs). These features
allow the devices to be used in low-cost, high-volume consumer and system applications.
The iCE40 devices are fabricated on a 40 nm CMOS low power process. The device architecture has several fea-
tures such as programmable low-swing differential I/Os and the ability to turn off on-chip PLLs dynamically. These
features help manage static and dynamic power consumption, resulting in low static power for all members of the
family. The iCE40 devices are available in two versions – ultra low power (LP) and high performance (HX) devices.
The iCE40 FPGAs are available in a broad range of advanced halogen-free packages ranging from the space sav-
ing 2.5x2.5 mm micro chip-scale BGA to the PCB-friendly 20x20 mm TQFP. Table 1-1 shows the LUT densities,
package and I/O options, along with other key parameters.
The iCE40 devices offer enhanced I/O features such as pull-up resistors. Pull-up features are controllable on a
“per-pin” basis.
The iCE40 devices also provide flexible, reliable and secure configuration from on-chip NVCM. These devices can
also configure themselves from external SPI Flash or be configured by an external master such as a CPU.
Lattice provides a variety of design tools that allow complex designs to be efficiently implemented using the iCE40
family of devices. Popular logic synthesis tools provide synthesis library support for iCE40. Lattice design tools use
the synthesis tool output along with the user-specified preferences and constraints to place and route the design in
the iCE40 device. These tools extract the timing from the routing and back-annotate it into the design for timing ver-
ification.
Lattice provides many pre-engineered IP (Intellectual Property) modules, including a number of reference designs,
licensed free of charge, optimized for the iCE40 FPGA family. By using these configurable soft core IP cores as
standardized blocks, users are free to concentrate on the unique aspects of their design, increasing their productiv-
ity.
100 VQFP
(14 x 14mm, 0.5mm)
121 ucBGA
(5 x 5mm, 0.4mm)
121 csBGA
(6 x 6mm, 0.5mm)
132 csBGA
(8 x 8mm, 0.5mm)
144 TQFP
(20 x 20mm, 0.5mm)
225 ucBGA
(7 x 7mm, 0.4mm)
256-ball caBGA
(14 x 14mm, 0.8mm)
1. No PLL available on the 36 ucBGA, 81 csBGA, 84 QFN and 100 VQFP packages.
2. Only one PLL available on the 81 ucBGA package.
Package
CM121
CM225
VQ100
CB121
CB132
TQ144
CT256
Code
LP384
95 (12)
92 (12)
LP1K
Programmable I/O: Max Inputs (LVDS25)
1-2
167 (20)
93 (13)
LP4K
178 (23)
93 (13)
LP8K
iCE40 LP/HX Family Data Sheet
95(11)
96(12)
HX1K
72(9)
1
107(14)
95(12)
HX4K
Introduction
178(23)
206(26)
95(12)
HX8K