iCE40LP1K-CM36TR Lattice, iCE40LP1K-CM36TR Datasheet - Page 34

• Manufacturer Part Number: iCE40LP1K-CM36TR
• Description: FPGA - Field Programmable Gate Array iCE40LP 1280 LUTs, 1.2V Ultra Low-Power
• Manufacturer: Lattice

Specifications of iCE40LP1K-CM36TR

• Rohs: yes

Switching Test Conditions
Figure 3-7 shows the output test load used for AC testing. The specific values for resistance, capacitance, voltage,
and other test conditions are shown in Table 3-4.
Figure 3-7. Output Test Load, LVCMOS Standards
Table 3-4. Test Fixture Required Components, Non-Terminated Interfaces
LVCMOS settings (L -> H, H -> L)
LVCMOS 3.3 (Z -> H)
LVCMOS 3.3 (Z -> L)
Other LVCMOS (Z -> H)
Other LVCMOS (Z -> L)
LVCMOS (H -> Z)
LVCMOS (L -> Z)
Note: Output test conditions for all other interfaces are determined by the respective standards.
Test Condition
DUT
188
R

1
V
R1
T
3-21
0 pF
0 pF
C
L
CL
LVCMOS 3.3 = 1.5V
LVCMOS 2.5 = V
LVCMOS 1.8 = V
1.5
1.5
V
V
V
V
CCIO
CCIO
OH
OL
- 0.15
- 0.15
Test Poi n t
/2
/2
Timing Reference
DC and Switching Characteristics
iCE40 LP/HX Family Data Sheet
CCIO
CCIO
/2
/2
V
V
V
V
V
V
V
—
—
—
OH
OH
OH
OL
OL
OL
T