S25FL128SAGMFI011 Spansion, S25FL128SAGMFI011 Datasheet - Page 71

• Manufacturer Part Number: S25FL128SAGMFI011
• Description: Flash 128Mb 3V 133MHz Serial NOR Flash
• Manufacturer: Spansion

Specifications of S25FL128SAGMFI011

• Rohs: yes

July 12, 2012 S25FL128S_256S_00_05
 The password is all 1’s when shipped from Spansion. It is located in its own memory space and is
 All 64-bit password combinations are valid as a password.
 The Password Mode, once programmed, prevents reading the 64-bit password and further password
 The Protection Mode Lock Bits are not erasable.
 The exact password must be entered in order for the unlocking function to occur. If the password unlock
 The Password Unlock command cannot be accepted any faster than once every 100 µs ± 20 µs. This
 If the password is lost after selecting the Password Mode, there is no way to set the PPB Lock bit.
accessible through the use of the Password Program and Password Read commands.
programming. All further program and read commands to the password region are disabled and these
commands are ignored. There is no means to verify what the password is after the Password Mode Lock
Bit is selected. Password verification is only allowed before selecting the Password Protection mode.
command provided password does not match the hidden internal password, the unlock operation fails in
the same manner as a programming operation on a protected sector. The P_ERR bit is set to one and the
WIP Bit remains set. In this case it is a failure to change the state of the PPB Lock bit because it is still
protected by the lack of a valid password.
makes it take an unreasonably long time (58 million years) for a hacker to run through all the 64-bit
combinations in an attempt to correctly match a password. The Read Status Register 1 command may be
used to read the WIP bit to determine when the device has completed the password unlock command or is
ready to accept a new password command. When a valid password is provided the password unlock
command does not insert the 100 µs delay before returning the WIP bit to zero.
D a t a
S25FL128S and S25FL256S
S h e e t
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