S25FL128SAGMFI011 Spansion, S25FL128SAGMFI011 Datasheet - Page 97

• Manufacturer Part Number: S25FL128SAGMFI011
• Description: Flash 128Mb 3V 133MHz Serial NOR Flash
• Manufacturer: Spansion

Specifications of S25FL128SAGMFI011

• Rohs: yes

July 12, 2012 S25FL128S_256S_00_05
10.4.5
SCLK
CS#
IO0
IO1
IO2
IO3
7
0
Dual I/O Read (DIOR BBh or 4DIOR BCh)
The instruction
 BBh (ExtAdd=0) is followed by a 3-byte address (A23-A0) or
 BBh (ExtAdd=1) is followed by a 4-byte address (A31-A0) or
 BCh is followed by a 4-byte address (A31-A0)
The Dual I/O Read commands improve throughput with two I/O signals — IO0 (SI) and IO1 (SO). It is similar
to the Dual Output Read command but takes input of the address two bits per SCK rising edge. In some
applications, the reduced address input time might allow for code execution in place (XIP) i.e. directly from
the memory device.
The maximum operating clock frequency for Dual I/O Read is 104 MHz.
For the Dual I/O Read command, there is a latency required after the last address bits are shifted into SI and
SO before data begins shifting out of IO0 and IO1. There are different ordering part numbers that select the
latency code table used for this command, either the High Performance LC (HPLC) table or the Enhanced
High Performance LC (EHPLC) table. The HPLC table does not provide cycles for mode bits so each Dual I/
O Read command starts with the 8 bit instruction, followed by address, followed by a latency period.
This latency period (dummy cycles) allows the device internal circuitry enough time to access data at the
initial address. During the dummy cycles, the data value on SI and SO are “don’t care” and may be high
impedance. The number of dummy cycles is determined by the frequency of SCK
Codes for SDR Enhanced High Performance on page
in the Configuration Register (CR1).
The EHPLC table does provide cycles for mode bits so a series of Dual I/O Read commands may eliminate
the 8-bit instruction after the first Dual I/O Read command sends a mode bit pattern of Axh that indicates the
following command will also be a Dual I/O Read command. The first Dual I/O Read command in a series
starts with the 8-bit instruction, followed by address, followed by four cycles of mode bits, followed by a
latency period. If the mode bit pattern is Axh the next command is assumed to be an additional Dual I/O Read
command that does not provide instruction bits. That command starts with address, followed by mode bits,
followed by latency.
The Enhanced High Performance feature removes the need for the instruction sequence and greatly
improves code execution (XIP). The upper nibble (bits 7-4) of the Mode bits control the length of the next Dual
I/O Read command through the inclusion or exclusion of the first byte instruction code. The lower nibble (bits
3-0) of the Mode bits are “don’t care” (“x”) and may be high impedance. If the Mode bits equal Axh, then the
device remains in Dual I/O Enhanced High Performance Read Mode and the next address can be entered
(after CS# is raised high and then asserted low) without the BBh or BCh instruction, as shown in
Figure
the device from Dual I/O Enhanced High Performance Read mode; after which, the device can accept
standard SPI commands:
1
6
10.36; thus, eliminating eight cycles for the command sequence. The following sequences will release
2
5
Instruction
3
4
Figure 10.32 Quad Output Read Command Sequence
4
3
(4-byte Address, 6Ch or 6Bh [ExtAdd=1], LC=11b)
5
2
D a t a
6
1
S25FL128S and S25FL256S
S h e e t
7
0
31
8
32 Bit Address
38
1
61). The number of dummy cycles is set by the LC bits
39
0
40
5
6
7
Data 1
4
41
0
1
2
3
42
4
5
6
7
Data 2
43
0
1
2
3
(Table 8.12, Latency
44
4
5
6
7
Data 3
45
0
1
2
3
46
4
5
6
7
Data 3
47
0
1
2
3
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