MAX9240GTM+ Maxim Integrated, MAX9240GTM+ Datasheet - Page 21

• Manufacturer Part Number: MAX9240GTM+
• Description: Serializers & Deserializers - Serdes 28Bit GMSL Deserializer
• Manufacturer: Maxim Integrated

Specifications of MAX9240GTM+

• Rohs: yes

Figure 9. Lock Time
The MAX9240 deserializer, when paired with the
MAX9271 or MAX9273 serializer, provides the full set of
operating features, but offers basic functionality when
paired with any GMSL serializer.
The deserializer has a maximum serial-bit rate of 1.5Gbps
for 15m or more of cable and operates up to a maximum
output clock of 50MHz in 25-bit, single-output mode, or
75MHz to 100MHz in 15-bit /11-bit, double-output mode,
respectively. This bit rate and output flexibility support
a wide range of displays, from QVGA (320 x 240) to
WVGA (800 x 480) and higher with 18-bit color, as well as
megapixel image sensors. Input equalization, combined
with GMSL serializer pre/deemphasis, extends the cable
length and enhances link reliability
The control channel enables a FC to program the serial-
izer and deserializer registers and program registers on
peripherals. The control channel is also used to configure
and access the GPIO. The FC can be located at either
end of the link, or when using two FCs, at both ends.
Two modes of control-channel operation are available.
Base mode uses either I
while bypass mode uses a user-defined UART protocol.
UART protocol allows full-duplex communication, while
I
Spread spectrum is available to reduce EMI on the paral-
lel output. The serial input complies with ISO 10605 and
IEC 61000-4-2 ESD protection standards.
Maxim Integrated
2
C allows half-duplex communication.
6.25MHz to 100MHz, 25-Bit GMSL Deserializer for
IN+ - IN-
LOCK
PWDN MUST BE HIGH
Coax or STP Cable With Line Fault Detect
Detailed Description
2
t
LOCK
C or GMSL UART protocol,
V
OH
Figure 10. Power-Up Delay
Registers set the operating conditions of the deserializer
and are programmed using the control channel in base
mode. The deserializer holds its device address and the
device address of the serializer it is paired with. Similarly,
the serializer holds its device address and the address of
the deserializer. Whenever a device address is changed,
the new address should be written to both devices. The
default device address of the deserializer is set by the
CX/TP input and the default device address of any GMSL
serializer is 0x80 (see
0x00 and 0x01 in both devices hold the device addresses.
The parallel output functioning and width depend on
settings of the double-/single-output mode (DBL), HS/VS
encoding (HVEN), error correction used (EDC), and bus
width (BWS) pins.
pin settings. Unused output bits are pulled low.
The parallel output has two output modes: single and
double output. In single-output mode, the deserialized
parallel data is clocked out every PCLKOUT cycle. The
device accepts pixel clocks from 6.25MHz to 50MHz
(Figures 11
In double-output mode, the device splits deserialized
data into two half-sized words that are output at twice the
serial-word rate
rializer use pixel clock rates from 33.3MHz to 100MHz
for 11-bit, double-output mode and 25MHz to 75MHz for
15-bit, double-output mode.
IN+/-
LOCK
PWDN
and 12).
(Figures 13
Table 2
Table 1
lists the bit map for the control
V
IH1
and 14). The serializer/dese-
t
PU
and
Register Mapping
MAX9240
Table
8). Registers
Bit Map
V
OH
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