MAX9240GTM+ Maxim Integrated, MAX9240GTM+ Datasheet - Page 29

• Manufacturer Part Number: MAX9240GTM+
• Description: Serializers & Deserializers - Serdes 28Bit GMSL Deserializer
• Manufacturer: Maxim Integrated

Specifications of MAX9240GTM+

• Rohs: yes

Figure 17. GMSL UART Data Format for Base Mode
Figure 18. SYNC Byte (0x79)
As shown in
packets going to or coming from the peripherals from
UART format to I
device removes the byte number count and adds or
receives the ACK between the data bytes of I
bit rate is the same as the UART bit rate.
The serializer/deserializer UART-to-I
interface with devices that do not require register address-
es, such as the MAX7324 GPIO expander. In this mode,
the I
directly reads/writes the subsequent data bytes
21). Change the communication method of the I
ter using the I2CMETHOD bit. I2CMETHOD = 1 sets
command-byte-only mode, while I2CMETHOD = 0 sets
normal mode where the first byte in the data stream is
the register address.
In bypass mode, the serializer/deserializer ignore UART
commands from the FC and the FC communicates with
the peripherals directly using its own defined UART pro-
tocol. The FC cannot access the serializer/deserializer
registers in this mode. Peripherals accessed through the
forward control channel using the UART interface need
to handle at least one PCLKOUT period Q 10ns of jitter
due to the asynchronous sampling of the UART signal
by PCLKOUT. Set MS/HVEN = high to put the control
channel into bypass mode. For applications with the FC
Maxim Integrated
START
6.25MHz to 100MHz, 25-Bit GMSL Deserializer for
2
C master ignores the register address byte and
D0
1
Figure
D1
0
START
2
C format and vice versa. The remote
D2
0
20, the remote-side device converts
Coax or STP Cable With Line Fault Detect
Interfacing Command-Byte-Only
D3
1
D0
FRAME 1
D4
1
I
D5
2
1
C Devices with UART
D1
UART Bypass Mode
2
D6
C conversion can
1
STOP
D2
D7
0
2
PARITY STOP
C. The I
2
START
C mas-
(Figure
D3
1 UART FRAME
2
C
D4
FRAME 2
Figure 19. ACK Byte (0xC3)
connected to the deserializer, there is a 1ms wait time
between setting MS/HVEN high and the bypass con-
trol channel being active. There is no delay time when
switching to bypass mode when the FC is connected to
the serializer. Do not send a logic-low value longer than
100Fs to ensure proper GPO functionality. Bypass mode
accepts bit rates down to 10kbps in either direction. See
the
tions. The control-channel data pattern should not be
held low longer than 100Fs if GPI control is used.
In I
face sends and receives data through an I
2-wire interface. The interface uses a serial-data line
(SDA) and a serial-clock line (SCL) to achieve bidirec-
tional communication between master and slave(s). A FC
master initiates all data transfers to and from the device
and generates the SCL clock that synchronizes the data
transfer. When an I
device’s control-channel port, the remote-side device’s
control-channel port becomes an I
faces with remote-side I
must accept clock stretching, which is imposed by the
deserializer (holding SCL low). The SDA and SCL lines
operate as both an input and an open-drain output. Pullup
resistors are required on SDA and SCL. Each transmission
consists of a START condition
followed by the device’s 7-bit slave address plus a R/W
bit, a register address byte, one or more data bytes, and
finally a STOP condition.
2
START
GPO/GPI Control
C-to-I
D5
D0
2
1
C mode, the deserializer’s control-channel inter-
D6
D1
1
STOP
D2
0
2
C transaction starts on the local-side
D7
START
section for GPI functionality limita-
D3
0
2
C perhipherals. The I
PARITY
D4
0
(Figure
D5
0
FRAME 3
MAX9240
STOP
2
C master that inter-
D6
1
5) sent by a master,
I
2
D7
1
C Interface
2
C-compatible
PARITY STOP
2
C master
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