MAX9240GTM+ Maxim Integrated, MAX9240GTM+ Datasheet - Page 40

• Manufacturer Part Number: MAX9240GTM+
• Description: Serializers & Deserializers - Serdes 28Bit GMSL Deserializer
• Manufacturer: Maxim Integrated

Specifications of MAX9240GTM+

• Rohs: yes

The GPI/GPO provides a simple solution for camera
applications that require a frame sync signal from the
ECU (e.g., surround-view systems). Connect the ECU
frame sync signal to the GPI input, and connect the GPO
output to the camera frame sync input. GPI/GPO have
a typical delay of 275Fs. Skew between multiple GPI/
GPO channels is 115Fs (max). If a lower skew signal is
required, connect the camera’s frame sync input to one
of the GMSL deserializer’s GPIOs and use an I
cast write command to change the GPIO output state.
This has a maximum skew of 1.5Fs.
Both the serializer and the deserializer have program-
mable device addresses. This allows multiple GMSL
devices, along with I
same control channel. The serializer device address
is in register 0x00 of each device, while the deserial-
izer device address is in register 0x01 of each device.
To change a device address, first write to the device
whose address changes (register 0x00 of the serializer
for serializer device address change, or register 0x01 of
the deserializer for deserializer device address change).
Then write the same address into the corresponding reg-
ister on the other device (register 0x00 of the deserializer
for serializer device address change, or register 0x01 of
the serializer for deserializer device address change).
CX/TP is a three-level input that controls the serial-
interface configuration and power-up defaults. Connect
Table 11. MAX9240 Feature Compatibility
Maxim Integrated
HSYNC/VSYNC encoding
Hamming-code error correction
I
CRC error detection
Double output
Coax
I
2
2
C-to-I
S encoding
6.25MHz to 100MHz, 25-Bit GMSL Deserializer for
MAX9240 FEATURE
2
C
Three-Level Configuration Inputs
Coax or STP Cable With Line Fault Detect
2
C peripherals, to coexist on the
of the Device Addresses
Providing a Frame Sync
Software Programming
(Camera Applications)
If feature not supported in the serializer, must be turned off in the deserializer.
If feature not supported in the serializer, must be turned off in the deserializer.
If feature not supported in the serializer, must use UART-to- I
If feature not supported in the serializer, must be turned off in the deserializer.
If feature not supported in the serializer, the data is inputted as a single word at 1/2 the output
frequency.
If feature not supported in the deserializer, must connect unused serial output through 200nF
and 50I in series to AVDD and set the reverse control-channel amplitude to 100mV.
If feature is supported in the serializer, must disable I
2
C broad-
CX/TP through a pullup resistor to IOVDD to set a high
level, a pulldown resistor to GND to set a low level, or
IOVDD/2 or open to set a midlevel. For digital control,
use three-state logic to drive the three-level logic input.
The deserializer can block changes to registers. Set
CFGBLOCK to make all registers read only. Once set,
the registers remain blocked until the supplies are
removed or until PWDN is low.
The MAX9240 deserializer is designed to pair with the
MAX9271/MAX9273 serializers, but interoperate with any
GMSL serializers. See the
The deserializer has two open-drain GPIOs available
when not used as configuration inputs. GPIO1OUT and
GPIO0OUT (0x0E, D3 and D1) set the output state of the
GPIOs. Setting the GPIO output bits to 0 pulls the output
low, while setting the bits to 1 leaves the output undriven
and pulled high through internal/external pullup resistors.
The GPIO input buffers are always enabled. The input
states are stored in GPIO1 and GPIO0 (0x0E, D2 and
D0). Set GPIO1OUT/GPIO0OUT to 1 when using GPIO1/
GPIO0 as an input.
The deserializer staggers the parallel data outputs to
reduce EMI and noise. Staggering outputs also reduces
the power-supply transient requirements. By default, the
deserializer staggers outputs according to
Disable output staggering through the DISSTAG bit
(0x08, D3).
GMSL DESERIALIZER
Compatibility with other GMSL Devices
2
S in the serializer.
Staggered Parallel Outputs
2
Table 11
C or UART-to-UART.
Configuration Blocking
for operating limitations.
MAX9240
Table
GPIOs
12.
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