C8051F714-GMR Silicon Labs, C8051F714-GMR Datasheet - Page 197
![no-image](/images/no-image-200.jpg)
C8051F714-GMR
Manufacturer Part Number
C8051F714-GMR
Description
8-bit Microcontrollers - MCU 8kB ADC Cap Sense
Manufacturer
Silicon Labs
Datasheet
1.C8051F709-GQR.pdf
(306 pages)
Specifications of C8051F714-GMR
Rohs
yes
Core
8051
Processor Series
C8051
Data Bus Width
8 bit
- Current page: 197 of 306
- Download datasheet (2Mb)
SFR Definition 28.11. P0DRV: Port 0 Drive Strength
SFR Address = 0xF9; SFR Page = F
SFR Definition 28.12. P1: Port 1
SFR Address = 0x90; SFR Page = All Pages; Bit Addressable
Name
Reset
Name
Reset
Bit
7:0
Bit
7:0
Type
Type
Bit
Bit
P1[7:0]
P0DRV[7:0]
Name
Name
7
0
7
1
Port 1 Data.
Sets the Port latch logic
value or reads the Port pin
logic state in Port cells con-
figured for digital I/O.
Drive Strength Configuration Bits for P0.7–P0.0 (respectively).
Configures digital I/O Port cells to high or low output drive strength.
0: Corresponding P0.n Output has low output drive strength.
1: Corresponding P0.n Output has high output drive strength.
6
6
0
1
Description
5
0
5
1
Rev. 1.0
0: Set output latch to logic
LOW.
1: Set output latch to logic
HIGH.
4
0
4
1
P0DRV[7:0]
P1[7:0]
R/W
R/W
Function
Write
3
0
3
1
C8051F70x/71x
2
0
2
1
0: P1.n Port pin is logic
LOW.
1: P1.n Port pin is logic
HIGH.
1
0
1
1
Read
0
0
0
1
197
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