C8051F714-GMR Silicon Labs, C8051F714-GMR Datasheet - Page 89
C8051F714-GMR
Manufacturer Part Number
C8051F714-GMR
Description
8-bit Microcontrollers - MCU 8kB ADC Cap Sense
Manufacturer
Silicon Labs
Datasheet
1.C8051F709-GQR.pdf
(306 pages)
Specifications of C8051F714-GMR
Rohs
yes
Core
8051
Processor Series
C8051
Data Bus Width
8 bit
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SFR Definition 15.2. CS0CF: Capacitive Sense Configuration
SFR Address = 0x9E; SFR Page = 0
Name
Reset
Bit
6:4
2:0
Type
7
3
Bit
CS0ACU[2:0]
CS0CM[2:0]
Unused
Unused
Name
R
7
0
Read = 0b; Write = Don’t care
CS0 Start of Conversion Mode Select.
000: Conversion initiated on every write of 1 to CS0BUSY.
001: Conversion initiated on overflow of Timer 0.
010: Conversion initiated on overflow of Timer 2.
011: Conversion initiated on overflow of Timer 1.
100: Conversion initiated on overflow of Timer 3.
101: Reserved.
110: Conversion initiated continuously after writing 1 to CS0BUSY.
111: Auto-scan enabled, conversions initiated continuously after writing 1 to
CS0BUSY.
Read = 0b; Write = Don’t care
CS0 Accumulator Mode Select.
000: Accumulate 1 sample.
001: Accumulate 4 samples.
010: Accumulate 8 samples.
011: Accumulate 16 samples
100: Accumulate 32 samples.
101: Accumulate 64 samples.
11x: Reserved.
R/W
6
0
CS0CM[2:0]
R/W
5
0
R/W
Rev. 1.0
4
0
Description
R
3
0
R/W
C8051F70x/71x
2
0
CS0ACU[2:0]
R/W
1
0
R/W
0
0
89
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