C8051F714-GMR Silicon Labs, C8051F714-GMR Datasheet - Page 46
C8051F714-GMR
Manufacturer Part Number
C8051F714-GMR
Description
8-bit Microcontrollers - MCU 8kB ADC Cap Sense
Manufacturer
Silicon Labs
Datasheet
1.C8051F709-GQR.pdf
(306 pages)
Specifications of C8051F714-GMR
Rohs
yes
Core
8051
Processor Series
C8051
Data Bus Width
8 bit
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C8051F70x/71x
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Notes:
General
Solder Mask Design
Stencil Design
Card Assembly
Dimension
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. This Land Pattern Design is based on the IPC-7351 guidelines.
3. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder
4. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used
5. The stencil thickness should be 0.125 mm (5 mils).
6. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pads.
7. A 2x2 array of 1.10 mm x 1.10 mm openings on a 1.30 mm pitch should be used for the center
8. A No-Clean, Type-3 solder paste is recommended.
9. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small
C1
C2
X1
E
mask and the metal pad is to be 60 µm minimum, all the way around the pad.
to assure good solder paste release.
pad.
Body Components.
Figure 8.2. QFN-24 Recommended PCB Land Pattern
Table 8.2. QFN-24 PCB Land Pattern Dimensions
3.90
3.90
0.20
Min
0.50 BSC
0.30
Max
4.00
4.00
Rev. 1.0
Dimension
X2
Y1
Y2
2.70
0.65
2.70
Min
Max
2.80
0.75
2.80
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